World of FPGA Podcast David Kirchner

Let us talk about simulations and their benefits for your FPGA development projects.



Content of this Episode:

* Simulations in general

* Simulations in FPGA development

* Benefits for your FPGA development projects

* How to start with simulations

* What are the boundaries of simulation

* Simulate a hole design or only modules



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We are looking back on 2023 and then we try an outlook into 2024.



Content of this Episode:

* Happy New Year and all the best for 2024

* Review of 2023

* some private facts

* Business

* Outlook into 2024

* Business

* Private things

* Next webinar in February 2024



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In addition to the last episode we will now have a look into the process of debugging an ARM core software.



Content of this Episode:

* Debugging an ARM (in a SoC)

* Use UART and printf

* Debug your bare metal application in Vitis

* Debug your Linux application in Vitis



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Let’s dive deeper into the debugging stuff. There are different ways of debugging an FPGA and the logic inside.



Content of this Episode:

* Debugging an FPGA

* Observe signal outputs

* Bring some internal signals to outer world

* Using a debug core

* Special case for ILA



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It was time for a little trip again. This time I went to Munich to the three-day FPGA conference of PLC2 and the Vogel Verlag.



Content of this Episode

* 3 day FPGA Conference in Munich

* A little insight

* My attended lectures

* Sessions on the first day

* Linux Build Methodologies: PetaLinux vs. Yocto Flow

* Coverage (aka Requirement Coverage)

* Using property descriptions to formally verify FPGA design code

* Synthesizing a Vivado Project on GitLab-CI and Deploying to an FPGA Board

* Secure method of enabling multiple design in FPGA

* Constraining Multiple Clock Domains

* AMD-Xilinx: Dynamic Function Exchange with Device Tree Overlay

* GDBServer in Hardware for VexRiscv Processing Systems

* Next Generation of High-Speed Interfaces for Vision Applications

* Sessions on the second day

* Demystify a Vitis Embedded Acceleration Platform

* MicroBlaze - A most flexible processor for FPGAs and MPSoCs

* Self organizing administration tool to control FPGA designs

* Fundamentals of Timing Analysis and Why No FPGA Design Can Do Without It

* How to crash 100+ AWS FPGA instances and how to insert Trojans into bitstreams

* Demonstration Setup for HashCache

* Sessions on the third day

* Do FPGA designers and hardware designers need to talk? A practical approach to shortening the project timeline

* How your FPGA design decisions affect PCB board performance

* Agilex SoC Architecture

* Turning your FPGA into a fast multichannel ADC

* PCIe, MIPI CSI-2, HDMI and DDR memory across platforms from an Open Source perspective

* Constant On-Time (COT) Control for FPGA High-Current Power Supplies

* Hardware attacks on FPGA: An overview of threats and security mechanisms



Next FPGA conference is from July 2nd to 4th, 2024



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To start up a Xilinx Zynq SoC many steps are required. To get an overview we will talk today about bootloader.



Content of this Episode

* Stage-0 Boot (also known as BootROM)

* First Stage Bootloader (FSBL)

* Second Stage Bootloader

* Linux Kernel

* Init



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