EUV The Focal Point

EUV The Focal Point - Team
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EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast. Industry Briefings: Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co. Focus Deep Dives: Unpack physics, plasma, optics and how EUV scanners really work. Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites. AI can make mistakes: always verify the information independently before using it as a basis for business decisions.

  1. VOR 1 TAG

    [036] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode is about a subtle but important shift in EUV. ASML and TSMC did not just post strong quarters; they showed that the next constraint is usable output, not headline access to advanced lithography. We look at the new productivity data, the tighter capacity plans, and why the industry is now trying to get more wafers from the same installed base. Key takeaways: - ASML reported Q1 2026 net sales of €8.8 billion, gross margin of 53.0%, and net income of €2.8 billion. - ASML raised full-year 2026 sales guidance to €36-40 billion and kept gross-margin guidance at 51-53%. - ASML released the NXE:3800E productivity package, increasing throughput from 220 to 230 wafers per hour at similar overlay. - ASML said High-NA has processed more than 500,000 wafers and achieved more than 80% availability. - TSMC reported 1Q26 revenue of US$35.9 billion, gross margin of 66.2%, and operating margin of 58.1%. - TSMC said 7nm and below accounted for 74% of wafer revenue in 1Q26, while HPC represented 61% of revenue by platform. - TSMC lifted its 2026 revenue outlook to above 30% growth in US-dollar terms and said capex should land at the high end of US$52-56 billion. - TSMC said N2 is ramping in Hsinchu and Kaohsiung, while new N3 capacity is planned for Tainan, Arizona, and Japan through 2028. - No new official Samsung or Intel EUV disclosures materially changed the week’s core picture, so the episode centers on ASML and TSMC. Glossary: Extreme Ultraviolet (EUV) — lithography using 13.5-nanometer light for advanced chip patterning. High Numerical Aperture (High-NA) — the next EUV optical generation with higher resolution and tighter patterning capability. Wafers per hour (WPH) — a scanner throughput metric showing how many wafers a tool can expose in an hour. Overlay — how accurately one patterned layer aligns with previous layers on the wafer. Installed Base Management — service, upgrades, field options, and support revenue from already deployed tools. N2 — TSMC’s 2-nanometer-class process family, including follow-on variants such as N2P and A16. High-performance computing (HPC) — processors and accelerators for data centers, artificial intelligence, and other compute-intensive workloads. Dynamic Random-Access Memory (DRAM) — volatile memory technology used in servers, PCs, mobile devices, and High Bandwidth Memory stacks.

    6 Min.

  2. 13. APR.

    [035] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at how artificial intelligence demand is feeding back into semiconductor manufacturing itself. Intel’s Terafab move, TSMC and Samsung’s new numbers, tighter equipment politics around China, and Japan’s fresh support for Rapidus all point to the same conclusion: EUV is now part of a wider manufacturing-system battle. The focus topic explains why fabs are using AI not only to sell chips, but to stabilize yield, shorten learning cycles, and make scarce lithography capacity more productive. Key takeaways - Intel formally joined Elon Musk’s Terafab effort with Tesla and SpaceX, turning a previously speculative foundry link into an announced partnership. - The proposed U.S. MATCH Act would extend pressure from already-banned EUV exports to DUV equipment sales and servicing, making support capacity itself a policy lever. - TSMC reported March 2026 revenue of NT$415.19 billion and first-quarter revenue of NT$1.134 trillion, up 35.1% year over year. - Samsung guided first-quarter 2026 sales of about 133 trillion won and operating profit of about 57.2 trillion won. - Samsung says it is feeding wafer-level pattern data back into design, using agentic AI for diagnostics, and running a Pyeongtaek fab digital twin on NVIDIA Omniverse. - Gartner forecasts 2026 semiconductor revenue at $1.3202 trillion, with memory revenue at $633.3 billion and meaningful pricing relief not expected until late 2027. - Japan approved another 631.5 billion yen for Rapidus, while Rapidus also announced NEDO approval for its FY2026 plan and opened new analysis and chiplet facilities. - One relevant thread remains unclear: Samsung’s reported 1 nm forksheet roadmap is still unofficial and should be treated as directional rather than confirmed. Glossary EUV — Extreme Ultraviolet lithography used for the most advanced patterning layers in semiconductor manufacturing. DUV — Deep Ultraviolet lithography, an older but still strategically important class of patterning tools. High-NA — High Numerical Aperture EUV, the next EUV platform aimed at higher resolution and fewer multi-patterning steps on critical layers. HBM — High Bandwidth Memory, a stacked memory architecture used heavily in AI accelerators. HBM4E — An expected enhanced generation of HBM4 with tighter quality and yield requirements for advanced memory production. Digital twin — A software-based virtual replica of a fab or process used for monitoring, simulation, and risk reduction. MES — Manufacturing Execution System software that tracks and coordinates production on the fab floor. PDK — Process Design Kit, the rule set and models chip designers need to design for a specific manufacturing process. Chiplet — A smaller die designed to be combined with other dies in an advanced package rather than built as one large monolithic chip. TAT — Turnaround Time, the elapsed time needed to move a design or wafer flow through a development or production cycle.

    6 Min.
  3. [034] Deep Dive Topic - Moore's law

    9. APR.

    [034] Deep Dive Topic - Moore's law

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Episode teaser Moore’s law is usually described as a promise that chips keep getting faster. This episode makes the case that the original idea was really an economic observation about how dense, useful circuitry could become cheaper to manufacture over time. We trace that story from the integrated circuit and the Intel 4004 through the Pentium, Apple’s M1, EUV lithography, and the modern AI accelerator era. Key takeaways - Moore’s law started as an economics-of-manufacturing idea, not a law of physics. - Its success depended on rising density, improving yields, larger wafers, and smarter circuit design. - Famous chips like the Intel 4004, 8086, and Pentium marked different commercial stages of the curve. - The end of easy voltage scaling broke the old link between more transistors and automatic clock-speed gains. - Modern progress increasingly comes from system integration, packaging, and workload-specific specialization. - EUV lithography helped extend advanced-node scaling, but it did not erase cost and yield trade-offs. - AI is now both a demand engine and a design target for the semiconductor roadmap. - The future of Moore’s law is broader and messier: less about one clean density curve, and more about useful computing per dollar and per watt. Glossary - Moore’s law — The long-run trend that economically useful chip complexity rises roughly exponentially over time. - Integrated circuit — A device that places many electronic components on one piece of semiconductor material. - Yield — The share of manufactured chips that work correctly and can be sold. - x86 — A processor family that became dominant in personal computers and many servers. - System on a chip — A chip that combines multiple major functions in one integrated design. - EUV lithography — A chip-patterning method that uses extremely short-wavelength light to print advanced features. - Chiplet — A smaller die designed to be combined with others inside one package. - Domain-specific accelerator — A processor block optimized for a particular workload, such as AI matrix operations.

    19 Min.

  4. 7. APR.

    [033] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode argues that EUV is becoming less of a pure lithography story and more of an infrastructure story. The most useful signals are commercial productization at Intel, long-duration power procurement at ASML, larger geographic ambition around TSMC, and policy moves that could affect the usable life of installed tools. It was a relatively light week for fresh scanner disclosures, so the emphasis is on economics, contracts, and industrial positioning. Key takeaways - Intel said its Core Ultra Series 3 with vPro is the first commercial PC platform built on Intel 18A, covering more than 125 business designs. - RWE expanded and extended its renewable power agreement with ASML to 130 megawatts through 2038. - The reported plan for TSMC to build 12 fabs, four packaging facilities, and an R&D center in Arizona remains unconfirmed and should be treated as rumor, not company guidance. - Reuters reported that proposed U.S. legislation would not only restrict certain chipmaking equipment sales to China but also halt servicing for named Chinese chipmakers. - SK hynix’s disclosed order for about 11.95 trillion won of ASML tools remains one of the clearest signs that memory makers are reserving future lithography capacity early. - Broadcom said TSMC capacity is a bottleneck in 2026 and that customers are increasingly signing multi-year supply agreements. - Broadcom’s new long-term deal to develop Google’s custom AI chips through 2031 shows that end-market demand is becoming more contractual and longer dated. - ASML said in its 2025 annual report that EUV revenue should increase significantly in 2026 because of advanced logic and DRAM demand. - This was a lighter week for brand-new EUV tool announcements, so some near-term uncertainty remains around exact fab and tool timelines. Glossary Extreme Ultraviolet (EUV) — Lithography that uses 13.5-nanometer light for the most advanced chip patterning. Deep Ultraviolet (DUV) — Older lithography technology that still handles a large share of commercial chip production. High Bandwidth Memory (HBM) — Stacked memory used heavily in artificial-intelligence accelerators and servers. Power Purchase Agreement (PPA) — A long-term contract to buy electricity at agreed terms. Advanced packaging — Methods that connect multiple chiplets or dies into one high-performance package. Installed base — The tools already operating at customer sites and generating output and service revenue. 18A — Intel’s leading-edge process generation now moving from launch claims into commercial products. Dynamic Random-Access Memory (DRAM) — Mainstream working memory used in servers, personal computers, and many other systems.

    4 Min.

  5. 31. MÄRZ

    [032] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode is a light-week update that focuses on what the newest factory and financing signals say about Extreme Ultraviolet lithography. The key story is not a dramatic new scanner milestone, but the spread of EUV into more geographies, more product classes, and more pre-committed capital. TSMC’s Japan approval, Intel’s commercial 18A launch, and SK hynix’s financing move all point in the same direction: EUV is becoming an operational replication problem. Key takeaways - Taiwan approved TSMC’s plan to bring 3nm production to its second Kumamoto fab, with equipment installation and mass production targeted for 2028. - Local reporting tied the approved Kumamoto 3nm plan to roughly 15,000 12-inch wafers per month of capacity. - Intel said Core Ultra Series 3 with vPro is the first commercial PC platform built on Intel 18A and is expected to support more than 125 designs. - SK hynix made a confidential filing for a U.S. listing that could raise roughly $9.6 billion to $14.4 billion, adding a financing angle to its recent EUV capacity push. - ASML said in its 2025 annual report that it expects EUV revenue to increase significantly in 2026 because of advanced logic and DRAM demand. - This was a light week for fresh EUV datapoints: there were no major new official High-NA yield, uptime, or shipment disclosures from ASML, Samsung, Micron, or Rapidus in the last seven days. Glossary Extreme Ultraviolet (EUV) lithography — A chip-patterning technology that uses 13.5-nanometer light for advanced semiconductor layers. High Numerical Aperture (High-NA) EUV — The next EUV platform generation, using a larger numerical aperture to improve resolution. 3nm — A leading-edge logic process class that uses EUV on critical layers, despite the name not matching a literal feature size. Intel 18A — Intel’s angstrom-era manufacturing node, using RibbonFET transistors and backside power delivery. Dynamic Random-Access Memory (DRAM) — Mainstream volatile memory used in servers, PCs, mobile devices, and as the base technology for HBM stacks. High Bandwidth Memory (HBM) — Stacked memory designed to feed very high data rates to artificial intelligence and high-performance accelerators. 12-inch wafer — The 300-millimeter silicon wafer format used for modern high-volume advanced chip production.

    5 Min.

  6. 24. MÄRZ

    [031] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks at how EUV demand is turning into explicit capital commitments instead of general roadmap talk. The headline items are SK hynix’s nearly $8 billion scanner order, imec’s High-NA EUV installation in Leuven, and the way AI memory and foundry partnerships are starting to reshape lithography demand. The bigger point is that the scarce resource is no longer just the machine. It is early access to the whole learning curve around the machine. Key takeaways - SK hynix disclosed a 11.95 trillion won purchase of EUV scanners from ASML Korea, with completion scheduled by December 31, 2027. - imec received an ASML EXE:5200 High-NA EUV system in Leuven and expects full qualification by Q4 2026. - The imec tool will support the NanoIC pilot line and gives ecosystem partners shared access to early High-NA process learning. - Samsung and AMD said they will align on primary HBM4 supply for AMD’s Instinct MI455X and also discuss a future foundry partnership. - Micron raised fiscal 2026 capital spending plans by $5 billion to more than $25 billion, with more increases expected in 2027. - Micron has started retrofitting the Tongluo P5 site in Taiwan, plans a second cleanroom there by the end of fiscal 2026, and expects meaningful shipments from the existing fab in fiscal 2028. - Broadcom said TSMC capacity is becoming a bottleneck into 2027, reinforcing the case for earlier capacity reservation across the AI supply chain. - Europe’s EUV leverage remains system-level: scanner integration, optics, source technology, and shared pilot-line process development. Glossary Extreme Ultraviolet (EUV) lithography — Chip patterning technology that uses 13.5-nanometer light to print very small features. High Numerical Aperture (High-NA) EUV — The next EUV generation with higher optical numerical aperture for tighter patterning and fewer multi-patterning steps. EXE:5200 — ASML’s High-NA EUV platform now being installed at selected early-access sites. High Bandwidth Memory 4 (HBM4) — A stacked memory generation designed for AI accelerators that need very high bandwidth and power efficiency. Pilot line — A shared development environment used to validate processes, materials, and integration before high-volume production. Cost per wafer — The effective manufacturing cost of processing one wafer, influenced by tool throughput, uptime, yield, and process complexity. Overlay — The accuracy with which one lithography layer is aligned to previous layers on the wafer. Laser-produced plasma (LPP) source — The EUV light source method in which lasers hit tin droplets to generate 13.5-nanometer radiation.

    15 Min.
  7. [030] Deep Dive Topic - Coordinated Manufacturability

    21. MÄRZ

    [030] Deep Dive Topic - Coordinated Manufacturability

    This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making. EUV lithography isn’t just a machine purchase. It’s an ecosystem-scale coordination problem with a balance sheet attached. This episode explains “coordinated manufacturability” in EUV terms: how chipmakers line up design, masks, materials, metrology, facilities, software, and service so that a quarter‑billion‑dollar bottleneck actually produces shippable chips. KEY TAKEAWAYS - EUV economics are dominated by fixed costs. The payback comes from sustained utilization, yield, and fast learning cycles. - A modern EUV scanner is priced in the hundreds of millions of dollars, and High‑NA tools are around $400 million each. - The “EUV bill” includes far more than scanners: masks, inspection, materials, fab utilities, and data infrastructure can bottleneck output. - Throughput and uptime are the biggest economic sensitivities in cost-of-ownership models. - Service, spares, and field upgrades are part of the EUV platform strategy, not an afterthought. - Faster cycle time accelerates learning. Learning speed is an economic variable, not just an engineering one. - Shared pilot lines and consortia reduce duplicated early learning and speed up ramps when frontier development costs explode. - Energy per wafer pass is now tracked as a performance metric, because utilities and cleanroom capacity can become limiting constraints. GLOSSARY - Coordinated manufacturability: Managing design and manufacturing as one economic system so bottlenecks don’t strand capital. - Cost of ownership (CoO): A framework that totals capital and operating costs per unit of useful output, sensitive to throughput and uptime. - Cost of technology: Industry shorthand for the total cost to produce a given generation of chips at target performance and yield. - Installed base management: Service, spares, upgrades, and support revenue tied to the installed fleet of lithography tools. - Field upgrade: A post-installation hardware/software upgrade that increases productivity or capability of an existing tool. - Mask set: The full collection of photomasks required to pattern a chip’s layers; a significant NRE (non-recurring engineering) cost. - Pilot line: A shared or dedicated facility for prototyping and de-risking process steps before mass production. - Uptime / availability: The fraction of time a tool is ready for productive operation; a key driver of effective capacity.

    22 Min.

  8. 17. MÄRZ

    [029] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. High-NA EUV moved closer to factory reality this week, but the bigger story is that AI demand is now reshaping the whole manufacturing stack around it. ASML supplied new readiness numbers, NVIDIA showed how AI is moving into lithography and verification flows, and Micron, SK hynix and Applied Materials made fresh moves around HBM, wafers and capacity. This episode explains why the competition is shifting from isolated tool milestones to coordinated manufacturability. Key takeaways - ASML said its High-NA EUV tools have processed about 500,000 wafers, are running at roughly 80% uptime, and target 90% uptime by the end of 2026. - NVIDIA said Samsung, SK hynix and TSMC are using GPU-accelerated software for semiconductor design and manufacturing; Samsung and SK hynix were specifically named in computational lithography and physical verification. - Micron said its 36GB 12H HBM4 is in high-volume production for NVIDIA Vera Rubin, with more than 2.8 TB/s bandwidth and about 20% better power efficiency. - Micron completed the acquisition of PSMC’s Tongluo P5 site in Taiwan and plans to retrofit the existing cleanroom now, with a second similar-sized cleanroom planned by the end of fiscal 2026. - Applied Materials said Micron and SK hynix will be founding partners at its EPIC Center, a planned $5 billion semiconductor equipment R&D effort. - SK Group Chairman Chey Tae-won said AI-driven wafer shortages could continue until 2030 and remain above 20% because HBM consumes large amounts of wafer capacity. - TSMC reported January-February 2026 revenue of NT$718.91 billion, up 29.9% year over year. - Public reporting still lacks customer-by-customer High-NA insertion dates, layer choices and product-specific deployment schedules. Glossary Extreme Ultraviolet (EUV) lithography — Advanced chip-patterning technology using 13.5 nm light for leading-edge semiconductor manufacturing. High Numerical Aperture (High-NA) EUV — The next EUV platform generation aimed at reducing process complexity and improving patterning economics at future nodes. High Bandwidth Memory (HBM) — Stacked DRAM used near AI accelerators to deliver very high memory bandwidth. HBM4 — The next major HBM generation, positioned for AI platforms such as NVIDIA Vera Rubin. Dynamic Random Access Memory (DRAM) — Mainstream volatile memory used in servers, PCs, mobile devices and the base dies behind HBM. Computational lithography — Software-intensive correction and optimization used to make mask patterns print accurately on wafers. Physical verification — Design checks that confirm a chip layout can be manufactured reliably under process rules. Advanced packaging — Technologies that connect or stack multiple chips closely to improve bandwidth, power and system performance. Uptime — The share of time a tool is available and operating as intended in a manufacturing environment. Cleanroom — A tightly controlled fabrication space designed to minimize particles, contamination and process variation.

    16 Min.
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EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast. Industry Briefings: Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co. Focus Deep Dives: Unpack physics, plasma, optics and how EUV scanners really work. Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites. AI can make mistakes: always verify the information independently before using it as a basis for business decisions.

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  • Erstellt von
    EUV The Focal Point - Team
  • Jahre aktiv
    2025 - 2026
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    36
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