Five Minute VHDL Podcast

Francesco Richichi

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Technology

Let's talk about hardware design using VHDL

05/18/2019

Q&A#10 RAM Parallelism

How I can parallelize a RAM in FPGA https://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/ Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses
05/13/2019

ep#22-Multiplier optimization

Learn how to optimize a multiplier in particular cases: For a technical analysis go to the post: https://surf-vhdl.link/OptimizationVhdl12b25 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses
04/28/2019

Ep#21-Serial-to-Parallel Parallel-to-Serial converter

Link to the post: https://surf-vhdl.link/99990 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve - https://www.francispreve.com
04/23/2019

Q&A#09-I need a clock!

In this podcast we will understand how to connect a clock signal to our FPGA Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses
04/10/2019

Q&A#08- What is the dithering

What is dithering? Where we can use this technique? Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve - https://www.francispreve.com
04/06/2019

ep#20-VHDL Generic

VHDL Generic Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve - https://www.francispreve.com
03/22/2019

Ep#19-Iterative statement

Even if the VHDL is not a software language, we can find a tyoica SW statement, the iterative statement. Let’s see how to use this https://t.me/SurfVhdl/92 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve - https://www.francispreve.com
03/18/2019

Ep#18-the conditional assignment in VHDL

Let’s understand how to implement a conditional statement in VHDL image for the episode http://t.me/SurfVhdl/86 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music by Francis Preve - https://www.francispreve.com

Let's talk about hardware design using VHDL

Creator

Francesco Richichi
Years Active

2019
Episodes

33
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Clean
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© Francesco Richichi
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Five Minute VHDL Podcast