EUV The Focal Point

EUV The Focal Point - Team
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EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast. Industry Briefings: Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co. Focus Deep Dives: Unpack physics, plasma, optics and how EUV scanners really work. Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites. AI can make mistakes: always verify the information independently before using it as a basis for business decisions.

  1. 1H AGO

    [024] Deep Dive Topic - Semiconductor types

    This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making. Logic chips think, graphics chips see, memory chips remember—but under the hood, they’re all transistors optimized for different constraints. In this episode we compare CPUs/SoCs, GPUs, and modern memory (SRAM, DRAM, NAND) through the lens of the EUV era: what the finished chips look like, what they’re used for, and why scaling shifts bottlenecks toward data movement and packaging. Key takeaways - “Logic” chips are dominated by wiring, power, and variability management—not just transistor switching speed. - CPUs optimize for latency and control; GPUs optimize for throughput and sustained data-parallel work. - SRAM is fast and refresh-free but expensive per bit, so it lives on logic dies as caches and registers. - DRAM is far denser but needs refresh, so it becomes main memory and the stacked memory used in HBM. - NAND flash is non-volatile storage that trades write/erase complexity and wear for ultra-low cost per bit. - EUV shows up in finished logic chips as higher density, enabling more compute, more cache, and more specialized accelerators. - EUV shows up in advanced DRAM as continued scaling, more bits per wafer, and improved power efficiency. - As compute gets denser, performance increasingly depends on moving data efficiently—making memory technology and packaging central. - HBM uses a wide, short-reach interface near the logic die to deliver extreme bandwidth with better energy per bit than long, high-speed board links. Glossary - Logic chip: A chip whose primary job is computation and control (CPUs, SoCs, accelerators). - GPU (graphics processing unit): A throughput-oriented logic chip built from many parallel compute blocks. - SRAM (static random access memory): Fast volatile memory built from bistable circuits; used mainly for on-chip cache. - DRAM (dynamic random access memory): Dense volatile memory that stores bits as charge and requires refresh. - NAND flash: Non-volatile memory used for storage; retains data without power by trapping charge. - GDDR: Graphics DRAM family commonly used as external memory on GPU add-in boards. - HBM (high bandwidth memory): 3D-stacked DRAM placed close to a logic die to provide very high bandwidth. - Chiplet: A design style that splits a system into multiple dies connected by high-speed package links. - Advanced packaging: Packaging technologies that integrate multiple dies closely (e.g., interposers and dense die-to-die links).

    20 min

  2. 3D AGO

    [023] Industry briefing - EUV The Focal Point

    *This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.* This week, Europe turns High-NA EUV from a roadmap slide into shared infrastructure as imec inaugurates NanoIC in Leuven. At the same time, Samsung switches from sampling to shipping HBM4, and capital plans from TSMC and Micron underline how tightly advanced nodes, packaging, and memory are now coupled. We close with a procurement reality check: when scarcity spreads beyond scanners, trust becomes an engineering variable. Key takeaways: - NanoIC launched at imec as Europe’s largest Chips Act pilot line, with a 2.5B euro investment package and major EU and national funding. - imec expects its first High-NA lithography tool to arrive in mid-March 2026, with reporting pointing to March 18. - NanoIC is positioned as an “EUV-ready” design-to-process loop, emphasizing PDKs, mask/data preparation, inspection, and defect learning speed. - Samsung says it has started shipping HBM4 to customers, claiming 11.7 Gbps consistent speed and a path to 13 Gbps. - HBM4 ramps translate into EUV load: more critical exposures, masks, resists, and metrology cycles needed to keep DRAM yields stable. - TSMC approved about $44.962B in capital appropriations spanning advanced technology, advanced packaging, and fab construction systems. - Micron’s New York megafab project progressed through January milestones, framed as a multi-decade, multi-fab domestic memory capacity hedge. - Claus Aasholm argues “trust, but verify” and supplier transparency matter most when leverage shifts during tight cycles. - Unclear: Samsung did not name HBM4 customers, and shipment volumes and yield trajectories were not disclosed. Glossary: EUV — Extreme Ultraviolet lithography using 13.5 nm light for advanced patterning. High-NA — High numerical aperture EUV optics (NA ~0.55) enabling higher resolution but new field/mask trade-offs. Numerical aperture (NA) — Optical parameter describing how much light an imaging system can accept; higher NA improves resolution. HBM4 — Sixth-generation high-bandwidth memory stack used near AI accelerators for very high throughput. PDK — Process Design Kit; a foundry/R&D-provided bundle of rules, models, and libraries for chip design. OPC — Optical Proximity Correction; computational steps that pre-distort mask patterns to print correctly on wafer. Pellicle — Thin membrane protecting EUV masks from particles, trading transmission for defect reduction. Defectivity — Rate and types of defects introduced during processing that impact yield and reliability. Digital twin — High-fidelity simulation model of a fab or tool used for optimization and predictive maintenance.

    15 min

  3. FEB 10

    [022] Industry briefing - EUV The Focal Point

    This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making. ASML’s latest results show EUV bookings still dominate the conversation, while High-NA starts to surface in routine reporting. ZEISS is pushing actinic mask qualification throughput with AIMS EUV 3.0, and TSMC’s Japan plan signals that leading-edge EUV operations may spread further. This week’s theme is simple: the fastest feedback loop wins. Key takeaways: - ASML reported Q4 2025 net bookings of €13.2B, including €7.4B in EUV, and said it recognized revenue for two High-NA systems. - ASML guided 2026 total net sales to €34–39B, signaling sustained tool demand. - ASML said it will streamline Technology and IT; Reuters reported the plan could involve about 1,700 job cuts. - ZEISS said AIMS EUV 3.0 is being deployed globally and delivers triple mask throughput versus the prior generation. - ZEISS highlighted Digital FlexIllu to emulate scanner illumination for both low-NA EUV and High-NA workflows on one system. - Reuters reported TSMC plans to mass-produce 3nm chips in Kumamoto, Japan; local media cited ~$17B investment while TSMC did not confirm the figure. - Be cautious with AI-generated investor commentary around Japan’s chip push; verify claims against primary statements and major wires. - Imec’s NanoIC pilot line released A14 logic and eDRAM pathfinding PDKs to support earlier design-technology co-optimization beyond 2nm. - MarketsandMarkets (via PR Newswire) forecast EUV lithography growing from $15.84B (2026) to $30.36B by 2032. - Unclear/publicly limited: customer-by-customer High-NA ramp schedules and mask defect printability budgets remain mostly non-disclosed. Glossary: EUV lithography — Extreme Ultraviolet lithography using ~13.5 nm light to pattern advanced semiconductor features. High-NA — High numerical aperture EUV (0.55 NA class) enabling higher resolution than 0.33 NA EUV systems. Numerical aperture — Optical parameter that sets resolution and depth of focus; higher NA increases resolution but tightens process margins. Actinic mask qualification — Mask inspection/verification at the exposure wavelength regime to assess defect printability under scanner-like conditions. AIMS — Aerial Image Measurement System; actinic tool used to evaluate EUV mask defect printability and scanner matching. Scanner matching — Aligning mask qualification conditions with scanner optics and illumination to predict wafer printing behavior. Illumination — The spatial/angular distribution of light used in exposure; affects imaging, process window, and defect printability. Overlay — Alignment accuracy between patterned layers; becomes more difficult as pitches shrink and depth of focus narrows. PDK — Process Design Kit; a set of design rules, device models, and flows enabling chip design for a given process technology. Design-technology co-optimization — Joint optimization of design rules, layouts, and process integration to reduce risk and improve manufacturability.

    14 min

  4. FEB 5

    [021] Deep Dive Topic - Semiconductor Technologies

    Modern chips are no longer “just smaller.” They’re built as 3D systems: memory stacked on logic, multiple chiplets stitched together in advanced packages, power delivered through the backside of the wafer, and—sometimes—data moved with light instead of copper. This episode tours the core technologies reshaping how high-performance processors are designed and manufactured. KEY TAKEAWAYS - HBM boosts bandwidth by stacking DRAM and using a very wide, short electrical interface near the compute die. - Next-gen GDDR boosts bandwidth by pushing much higher per-pin signaling over longer board traces, trading cost for harder signal integrity. - Advanced packaging has become part of architecture: interposers, bridges, fan-out, and true 3D stacking are performance tools now. - Chiplets improve yield and modularity, but shift the bottleneck to die-to-die interconnect and package-level thermal design. - Backside power delivery separates power routing from signal routing to relieve congestion and improve power integrity—at the cost of process complexity. - Gate-all-around nanosheets improve electrostatic control beyond FinFETs, enabling further logic scaling. - 2D materials like MoS2 and WSe2 look promising as ultra-thin channels, but manufacturable integration is still a major hurdle. - Optical interconnects and silicon photonics can cut the pain of long, high-bandwidth copper links, but electrical–optical conversion and packaging are the “optics tax.” GLOSSARY - HBM (High Bandwidth Memory): 3D-stacked DRAM with a very wide interface for high bandwidth and good energy efficiency. - GDDR: High-speed graphics DRAM used on PCBs; bandwidth scales mainly by higher per-pin data rates. - TSV (Through-Silicon Via): Vertical conductor through a die, enabling dense 3D connections in stacked devices. - 2.5D Packaging: Side-by-side dies connected by an interposer or bridge that provides very dense routing. - 3D Stacking: Vertical die integration; can be memory-on-logic or logic-on-logic. - Hybrid Bonding: Direct copper-to-copper (and oxide-to-oxide) bonding for very fine-pitch vertical interconnects. - Chiplet: A modular die used as a building block in a larger package-level system. - Backside Power Delivery: Power routing moved to the wafer backside to improve power integrity and free front-side routing resources. - GAA (Gate-All-Around): Transistor architecture where the gate surrounds the channel for strong electrostatic control. - Silicon Photonics: Optical components integrated with silicon manufacturing to enable high-bandwidth optical links near chips. This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

    18 min

  5. FEB 2

    [020] Industry briefing - EUV The Focal Point

    ASML’s Q4 2025 results turned the A.I. chip boom into a lithography backlog that looks more like a capacity reservation system than a sales pipeline. This week we connect that record order intake to the real factory constraint: usable exposures per day in Extreme Ultraviolet. Then we zoom out to the “memory wall” and why high-bandwidth memory demand feeds directly into E. U. V. tool time. Key takeaways: - ASML ended 2025 with a €38.8B backlog, and Q4 net bookings of €13.2B included €7.4B of E. U. V. systems. - ASML guided 2026 net sales to €34–39B with gross margin of 51–53%, signaling execution and fab readiness as key limiters. - A new ASML share buyback program of up to €12B through 2028 underscores confidence in multi-year demand visibility. - The “memory wall” is shifting system performance bottlenecks from compute to bandwidth and data movement, accelerating demand for HBM and server DRAM. - Rising HBM demand tends to increase E. U. V. intensity in advanced DRAM as pitches shrink and multi-patterning becomes less tolerable. - High-N. A. E. U. V. is moving from prototype to factory accountability, with ASML recognizing revenue for two High-N. A. systems in Q4. - In the A.I. era, the strategic variable is not just tool count but throughput, defectivity, and cycle time at the E. U. V. bottleneck. - Missing/unclear: Several major E. U. V. buyers have provided limited new, on-the-record near-term installation and ramp timelines beyond recent earnings disclosures. Glossary: Backlog — Accumulated value of accepted system orders not yet recognized as revenue. Net bookings — Order intake for systems (and related adjustments) accepted during a period. Extreme Ultraviolet (E. U. V.) lithography — 13.5 nm wavelength lithography used for leading-edge patterning. High numerical aperture (High-N. A.) — Higher-NA E. U. V. optics aimed at improved resolution and reduced multi-patterning. Throughput — Productive wafers per hour/day; the practical capacity metric at bottleneck tools. Stochastic variability — Random process noise that can cause line-edge roughness, defects, or yield loss at small features. Multi-patterning — Using multiple exposures/etch steps to achieve smaller pitch than a single lithography step can print. HBM — High-bandwidth memory, typically stacked DRAM used with accelerators to increase memory bandwidth. DDR5 — A mainstream server memory generation whose demand rises with inference-scale deployments. Installed base management — Service, options, and support revenue tied to the fleet of deployed tools. This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

    11 min

  6. JAN 28

    [019] Deep Dive Topic - Semiconductor KPI's

    EUV lithography is governed by operational currencies. From wafers per hour to stochastic defect rates and downtime cost, these KPIs define what is technically possible and economically viable. This episode decodes the most important EUV-relevant metrics and their trade-offs. Key Takeaways - WPH reflects physics, chemistry, and system efficiency - Availability often matters more than peak throughput - EUV yield is limited by stochastic effects - Dose links pattern quality to productivity - Downtime cost strongly shapes EUV economics Glossary WPH: Wafers processed per hour OEE: Overall equipment effectiveness Overlay: Layer-to-layer alignment accuracy DOF: Depth of focus tolerance COO: Cost of ownership This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

    16 min

  7. JAN 27

    [018] Industry briefing - EUV The Focal Point

    This week, the EUV story is less about new nodes and more about operational reality: tool installs, uptime, and the painful gap between “first light” and stable yield. Intel’s latest update underscores a tilt toward tool spending and a clearer tie between High-NA and its 14A roadmap. Meanwhile, reporting around Samsung’s Taylor site points to EUV test operations starting in March, as AI-driven memory demand keeps the whole lithography ecosystem under pressure. Key takeaways: - Intel says near-term manufacturing output is constrained, with improvement expected as tool additions, yield work, and throughput gains take hold. - Intel is signaling a 2026 spend mix that prioritizes manufacturing tools over new cleanroom shell expansion. - Intel confirms High-NA EUV is targeted for its 14A process family, turning High-NA from a technology demo into a roadmap assumption. - Reports say Samsung will begin EUV tool test operations at its Taylor, Texas foundry site in March, ahead of planned H2 2026 production. - The Taylor reports also cite roughly 7,000 workers on-site daily and a push for temporary occupancy clearance, highlighting the “factory readiness” side of EUV. - Reuters reports Samsung plans to start HBM4 production next month for intended Nvidia supply, reinforcing AI memory as a structural driver of advanced patterning capacity. - ASML’s Q4 and full-year 2025 results arrive January 28, a near-term read on EUV mix and High-NA cadence. - Some details around Samsung’s Taylor timing and end-customer allocations are based on third-party reporting and remain unconfirmed by official Samsung statements. Glossary: Extreme Ultraviolet (EUV) lithography — 13.5 nm-wavelength lithography used for leading-edge patterning. High-NA — High numerical aperture EUV optics that improve resolution but tighten process control demands. Numerical aperture — A measure of an optical system’s ability to resolve fine features. First light — The milestone when an EUV tool produces usable exposure performance at a site. Overlay — Layer-to-layer alignment accuracy; a key yield driver at advanced nodes. Pellicle — A thin membrane that protects the EUV mask from particles while transmitting EUV light. Stochastic effects — Random photon and chemistry variations that can cause defects at very small feature sizes. Throughput — Practical wafer output of a tool or line, often constrained by uptime and dose requirements. Yield — The fraction of good dies per wafer; the ultimate test of process stability. This podcast was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

    14 min

  8. JAN 22

    [017] Deep Dive Topic - Chip Manufacturing

    A modern chip looks simple from the outside, but it’s the end result of an industrial chain that starts with sand and ends with nanometer-accurate patterning in a cleanroom. In this episode we walk the full path, step by step, without over-focusing on any single stage. When we reach lithography, we use an EUV scanner as the concrete example. Key takeaways - Chipmaking is a repeating loop: add a film, pattern it, transfer it, measure it, and repeat. - Electronic-grade silicon often uses chlorosilane chemistry and distillation-based purification before silicon is redeposited as ultra-pure polysilicon. - Single-crystal ingots are grown (commonly by the Czochralski method) and sliced, polished, and flattened into wafers. - Cleaning and contamination control are as fundamental as any “core” process step. - Thin films are built by oxidation and deposition methods such as CVD, PVD, and ALD, each with different trade-offs. - EUV lithography uses 13.5 nm light, vacuum, and mirror optics; the light is generated by a tin plasma source. - Plasma etching translates resist patterns into device layers with trade-offs between selectivity, directionality, and uniformity. - Ion implantation and annealing create doped regions while balancing activation against thermal budget risks. - CMP keeps the wafer flat enough for lithography and multilayer integration, but introduces its own defect risks. - After BEOL wiring, wafers are tested, diced, packaged, and screened so only known-good parts ship. Glossary - Electronic-grade polysilicon: Ultra-pure polycrystalline silicon used as feedstock for crystal growth. - Czochralski growth: A method for pulling a single-crystal ingot from molten silicon using a seed crystal. - Photoresist: A light-sensitive polymer film used to form a temporary pattern during lithography. - EUV lithography: Patterning with 13.5 nm extreme ultraviolet light using reflective optics in vacuum. - Reticle (mask): The patterned template whose image is projected onto the wafer in a scanner. - Plasma etch (dry etch): Material removal in a plasma chamber using reactive species and ion bombardment. - Ion implantation: Doping by accelerating ions into a wafer to place impurities at controlled depth and dose. - Anneal: A thermal step used to repair damage and activate dopants or modify materials. - CMP: Chemical-mechanical planarization; a polishing step that restores wafer flatness. - BEOL: Back end of line; the multilayer metal interconnect stack that wires transistors together. This article was created with the help of AI. AI can make mistakes. Please verify the information if you intend to use it as a basis for your decision-making.

    13 min
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About

EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast. Industry Briefings: Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co. Focus Deep Dives: Unpack physics, plasma, optics and how EUV scanners really work. Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites. AI can make mistakes: always verify the information independently before using it as a basis for business decisions.

Information

  • Creator
    EUV The Focal Point - Team
  • Years Active
    2025 - 2026
  • Episodes
    24
  • Rating
    Clean
  • Copyright
    © EUV The Focal Point - Team
  • Show Website
    EUV The Focal Point