EUV The Focal Point

EUV The Focal Point - Team

EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast. Industry Briefings: Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co. Focus Deep Dives: Unpack physics, plasma, optics and how EUV scanners really work. Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites. AI can make mistakes: always verify the information independently before using it as a basis for business decisions.

  1. 11h ago

    [071] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Quarterly results turn the AI investment cycle into more specific procurement and manufacturing targets. This November 3, 2026 briefing examines why equipment revenue can grow faster than wafer capacity, and what that means for EUV suppliers. Key takeaways - SK hynix reported Q3 revenue of KRW 104.6 trillion; M15X is targeted to reach maximum capacity by end-2026. Contracts cover more than half of 2027–2028 production capacity. - Samsung forecasts 2026 semiconductor-division capital expenditure of KRW 76.8 trillion; this is a spending forecast, not an EUV equipment budget. - Intel's firm equipment purchase orders rose nearly 40% sequentially. It expects USD 20 billion gross capital expenditure in 2026 and a strong increase in 2027; Q4 revenue guidance is USD 15–16 billion versus Q3's USD 16.5 billion. - Intel's data-center and AI revenue rose 78% year on year, while client revenue fell 5%; demand differs by end market. - ASM reported EUR 1.159 billion revenue, up 44% at constant currencies, and projects more than EUR 5.7 billion in 2027 on that basis. It expects double-digit addressable-market growth at 1.4nm versus 2nm and higher market share. - KLA reported USD 4.136 billion revenue and guides the December quarter to USD 4.7 billion ± USD 0.2 billion. - Tokyo Electron reported quarterly sales of JPY 935 billion; its global WFE forecast is approximately USD 160 billion for calendar 2026 and over USD 210 billion for 2027. - Applied's October 26 agreement would raise its Besi stake to approximately 20%, subject to the antitrust waiting period. TrendForce's 10–20% CoWoS price-increase report remains unconfirmed by TSMC in the reviewed evidence. - Illustrative calculation, not company data: 10% more planned capacity multiplied by 20% more equipment spending per capacity unit gives a 32% larger equipment budget. - Watch Intel's 2027 budget and process allocation, M15X target execution, and the applications and shipments behind ASM's outlook. Glossary EUV — Extreme ultraviolet lithography. HBM — High Bandwidth Memory; HBM4 denotes the fourth generation. Capital expenditure — Investment in long-lived assets; equipment and buildings serve different stages of a ramp. WFE — Wafer fabrication equipment; a broad manufacturing-equipment category, not an EUV-only market. CoWoS — Chip on Wafer on Substrate, TSMC's advanced-packaging technology. Served available market — The part of a market addressable by a supplier's relevant products and applications. Constant currencies — Growth measured with exchange-rate effects held constant. Market share — A supplier's portion of sales in a defined market. Gross capital expenditure — Capital spending before specified offsets such as government incentives or partner contributions.

  2. Oct 26

    [070] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. New factory schedules and equipment orders show where semiconductor capacity is heading. TSMC's reported component review and Intel's temporary regulatory relief expose a different challenge: how quickly an alternative can be qualified for actual operation. The focus examines component substitution, retrofit decisions and recovery time. Key takeaways - Intel targets Fab 62 operations by end-2028; construction and tool installation are underway. Ohio One reached a structural-truss milestone. - Besi booked €342.6 million of Q3 orders, up 17% sequentially; Q4 revenue guidance is €283.4 million ±5%, with some deliveries aligned to H1 2027 capacity plans. - Musk targets Terafab volume production in Q3–Q4 2028 and an Austin test chip around Q2 2027; these remain uncertain ambitions. - Micron reached a Taichung union agreement; a small Taoyuan strike and rejection of a later proposal followed. The reports do not quantify lost wafer output. - Reuters reports early TSMC discussions on rare-earth-free automation motors, without broad deployment or an identified scanner-stage redesign. - Reuters reports a one-year FCC waiver for specified changes to Intel's existing foreign-made automated guided vehicles; the decision was on October 22. - Analysis: a credible alternative requires qualification and a realistic deployment time; supplier count alone cannot establish operational independence. - Outlook: Micron talks on October 27, Intel results on October 29, and evidence of an identified TSMC qualification or deployment program. Glossary EUV — Extreme ultraviolet lithography, used to pattern critical semiconductor layers. Hybrid bonding — Direct bonding of dielectric surfaces and metal contacts for dense chip interconnections. Automated guided vehicle — A vehicle that transports materials automatically within a facility. Qualification — Evidence that a component or system meets specified requirements for its intended use. Retrofit — Modification of equipment already installed and in operation. Lead time — Elapsed time between initiating a supply or implementation activity and its completion. Second source — An additional supplier or qualified supply route for a required function. Recovery time — Time required to restore an accepted operating function after disruption.

  3. Oct 19

    [069] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. ASML and TSMC provide new evidence on equipment supply and advanced-node demand. The focus examines how faster mask calculations can translate into shorter engineering schedules or better process margins, using an explicitly illustrative example. Key takeaways - ASML expects planned supply to fall short in 2027–2028 and is investigating 2028 capacity growth above 30%; no revised unit count is given in the release. - TSMC reported $46.72 billion quarterly revenue; 2nm and 3nm contributed 8% and 33% of wafer revenue, respectively. Revenue shares are not wafer-volume shares. - Microsoft's Maia 300 plan specifies N2P compute chiplets, eight HBM4 stacks and production deployments in 2027. - SEMI forecasts $149 billion of 300mm front-end equipment spending in 2026 and $227 billion in 2029; these are not EUV-specific forecasts. - Applied targets more than doubling research-laboratory and manufacturing capacity by 2030; EPIC capital spending is expected to scale toward approximately $5 billion. - Siemens reports up to 12x full-chip OPC acceleration and separately 10–17x selected simulation gains; the benchmark scopes differ. - NVIDIA reports an imec process-window improvement of 30% in a specific computational-lithography application; this is not a universal production guarantee. - Illustrative calculation: accelerating eight days of a ten-day workflow by 10x reduces total time to 2.8 days, approximately 3.6x faster overall. It is not a measured customer result. - The economic assessment must distinguish earlier readiness from additional optimization, and include implementation costs and measured wafer performance. Glossary EUV — Extreme ultraviolet lithography, used to pattern critical semiconductor layers. High-NA — High numerical aperture; an EUV optical platform with a higher numerical aperture. N2P — TSMC process designation for an enhanced generation of its 2nm technology family. HBM4 — Fourth-generation high-bandwidth memory. OPC — Optical proximity correction; mask adjustments that compensate for imaging distortions. ILT — Inverse lithography technology; computational optimization with greater freedom over mask geometry. Process window — The operating range within which a pattern meets specified acceptance criteria. EPIC — Equipment and Process Innovation and Commercialization Center. End-to-end benchmark — Measurement of an entire defined workflow rather than one accelerated calculation.

  4. Oct 19

    [068] Deep Dive Topic - ASML Q3 2026 DEEP-DIVE

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. ASML Q3 2026: EUV at the Center of a Record Quarter EPISODE TEASER ASML's third-quarter 2026 results combine record revenue with an unusual engineering challenge: the company believes planned equipment output in 2027 and 2028 will not fully meet customer demand. We unpack the full quarterly report, from margins and cash flow to DUV systems, upgrades, and regional sales, while focusing on EUV lithography. The deeper story is how scanner throughput, High NA optics, photomasks, and metrology determine the real cost of producing leading-edge chips. KEY TAKEAWAYS - ASML reported €11.662 billion in Q3 sales and a 57.5% gross margin; €4.960 billion net income included an approximately €0.5 billion revaluation gain related to its initial Mistral AI investment. - EUV generated about €4.1 billion of the €8.4 billion in system sales, including one High NA system; 17 EUV systems were sold in the quarter. - Installed Base Management contributed €3.289 billion. Demand for EUV and DUV productivity upgrades helped it exceed guidance and boosted gross margin. - Quarterly system sales were 54% logic and 46% memory. Shipment destinations were led by Taiwan and South Korea; China represented 23% of Q3 net system sales, not 23% of all revenue. - ASML expects approximately 65 Low NA EUV systems of output in 2026 and is exploring additional 2028 capacity because its current production plans are expected to fall short of demand. - The planned NXE:3800F boosts specified Low NA EUV throughput from 230 to 260 wafers per hour; actual fab output also depends on uptime, resist exposure dose, and the surrounding process flow. - High NA increases EUV numerical aperture from 0.33 to 0.55, improving optical resolution while reducing depth of focus and complicating exposure-field size and alignment. - Intel and ASML reported more than one million High NA wafers processed across R&D, certification, and selected volume production. Samsung and TSMC have separate future adoption targets. - ASML and TSMC are promoting larger-format EUV masks, targeting a pilot line in 2031 and production readiness by 2033. A slide's greater-than-40% potential productivity uplift is a future scenario, not Q3 realized performance. - ASML guided to €44–45 billion in full-year 2026 sales and around 56% gross margin. A large Q3 free-cash-flow figure benefited from customer down payments and should not be equated with earnings. GLOSSARY - EUV (extreme ultraviolet lithography): Pattern projection using 13.5-nanometer light and reflective optics in vacuum. - DUV (deep ultraviolet lithography): A family of shorter-wavelength ultraviolet scanners, including 193-nanometer immersion tools used on many chip layers. - Numerical aperture (NA): An optical system's ability to collect higher-angle diffracted light, affecting resolution and focus tolerance. - High NA EUV: EUV platform with 0.55 numerical aperture, versus 0.33 for the established Low NA EUV platform. - Photomask / reticle: A patterned optical element that carries the circuit image projected onto a wafer. - Anamorphic optics: Optics that reduce the reticle image by different factors along two axes. - Overlay: Alignment accuracy between newly patterned features and earlier wafer layers. - Throughput: Number of wafers a system can process within a specified time, often quoted as wafers per hour. - Installed Base Management: ASML revenue from net services and field options, including upgrades, for systems already deployed. - Stochastic defects: Random patterning failures associated with limited photon counts and the microscopic behavior of photoresist chemistry. SOURCES ASML Q3 2026 quarterly results hub — https://investor.asml.com/quarterly-results

    [068] Deep Dive Topic - ASML Q3 2026 DEEP-DIVE

  5. Oct 12

    [067] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. New TSMC and Samsung figures reinforce the scale of semiconductor demand, while GlobalFoundries adds a dated interposer-supply plan for TSMC. The focus examines the Hyper-NA study's principal unresolved constraint: a smaller focus budget and the need for thinner resists. Architectural reuse could limit transition spending, but the proposed optics are not a commercial production commitment. Key takeaways - TSMC reported September revenue of NT$511.86 billion, up 54.6% year on year and down 0.6% month on month; January–September revenue grew 41.1%. - Samsung's preliminary Q3 guidance projects KRW195 trillion in consolidated sales and KRW107.4 trillion in operating profit, versus KRW12.17 trillion profit a year earlier; these are estimates, not final or foundry-specific results. - SIA reported sales exceeding US$1 trillion through August; its August figure of US$159.7 billion, up 8% sequentially, uses a WSTS three-month moving average. - Reuters reported AMD's plan for a substantial 2027 supply increase and need for more advanced wafer capacity; no wafer-volume, node-allocation or new-fab commitment was disclosed in those comments. - GlobalFoundries announced a US$2 billion agreement with TSMC for CoWoS silicon interposers, an initial five-year term and an expected Malta, New York volume ramp in H1 2028; this is packaging-component capacity. - The October 1 Hyper-NA paper proposes at least 0.75 numerical aperture at 13.5 nm and approximately 5 nm optical half-pitch; its roughly ten-year development estimate is not a committed delivery date. - The study identifies an approximately halved idealized depth of focus versus 0.55 NA, motivating better focus control and thinner resists; actual process windows remain pattern-dependent. - Source reuse leaves future power needs open; polarization can improve contrast but introduces a photon penalty, and a proposed 0.75-NA micro-exposure tool could support resist development. - ASML and TSMC have Q3 results scheduled for October 14 and 15 respectively; watch output guidance, advanced-node capacity and packaging execution, alongside measured Hyper-NA resist/focus results. Glossary EUV — Extreme ultraviolet lithography; the proposal retains the 13.5 nm wavelength. High-NA — High numerical aperture EUV; the 0.55-NA platform used as the study's comparison. Hyper-NA — Proposed EUV architecture with numerical aperture of at least 0.75. Half-pitch — Half the repeat distance of a periodic pattern; distinct from a commercial node name. Depth of focus — Axial imaging tolerance; an idealized optical value is not a complete manufacturing process window. Resist — Photosensitive patterning film; thinning it changes photon absorption and pattern-transfer requirements. Edge-placement error — Difference between an intended pattern edge and its realized position. Micro-exposure tool — Small-field research exposure system for developing materials under future optical conditions. CoWoS — Chip on Wafer on Substrate, TSMC's advanced packaging platform.

  6. Oct 5

    [066] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Micron's September 30 results provide a concrete follow-up to last week's investment outlook, while Samsung projects a larger share of DRAM wafer capacity going to HBM. This episode examines how take-or-pay commitments improve investment visibility and why product mix, qualification and delivery timing still determine the EUV implications. Key takeaways - Micron reported fiscal Q4 2026 revenue of $54.23 billion and full-year net capital expenditure of $27.37 billion; financial growth is not a physical capacity measure. - Micron guides approximately $25 billion of net capex for the first half of fiscal 2027, with higher spending in the second half; $25 billion is not its full-year budget. - Samsung's Kim Taewoo expects HBM to use nearly 30% of industry DRAM wafer capacity in 2027, versus about 20% currently; this is an expectation, not market share or bit share. - Micron reports 26 multi-year take-or-pay SCAs, estimated to cover over 35% of revenue through 2030, with some agreements extending into 2031. - Micron identifies 1-gamma as its largest DRAM production node; its technology documentation confirms EUV use. - Micron says Singapore HBM packaging cleanroom preparation is ahead of plan, with initial output expected in early calendar 2027; packaging is distinct from front-end wafer capacity. - The September 28 outlook is partly answered on spending; a precise Micron HBM4E production date remains unestablished in the sources used here. - Analysis: translating contracted bits into exposure demand requires product mix, bits per wafer, yield and patterning-flow assumptions. - Fresh qualifying news was concentrated in memory; already-covered A14 pilot and silicon-wafer pricing reports were excluded from the news segment. Glossary EUV — Extreme ultraviolet lithography, used to pattern selected critical semiconductor layers. HBM — High Bandwidth Memory, a stacked DRAM product designed for high data bandwidth. DRAM — Dynamic Random-Access Memory, volatile memory used in computing systems. SCA — Strategic Customer Agreement; Micron uses this term for its multi-year customer supply arrangements. Take-or-pay — A contractual obligation to take an agreed quantity or make the required payment, subject to the agreement's terms. Net capex — Capital expenditure after the relevant offsets; Micron's guidance is net of anticipated government incentives. 1-gamma — Micron's EUV-enabled DRAM technology generation, also written 1γ. Front-end capacity — Wafer fabrication capacity, distinct from subsequent packaging and assembly. Qualification — Validation that a product or manufacturing process meets the relevant requirements before broader deployment.

  7. Sep 28

    [065] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. TSMC’s A14 program is becoming more operational: reported pilot timing is moving earlier while the design ecosystem is filling in with certified flows, interface IP and customer test-chip activity. At the same time, reported 300-millimeter wafer price pressure shows that AI-driven scarcity is moving deeper into the manufacturing supply chain. The EUV implication is important: more near-term pressure on the established EUV fleet does not mean TSMC is bringing High-NA production forward. Key takeaways - TrendForce reports that TSMC could begin A14 pilot production at Baoshan in 1Q27, while the company’s volume-production target remains 2028. - Cadence and Synopsys announced certified EDA flows for TSMC A14 at the 2026 North America OIP Ecosystem Forum. - Cadence says UCIe-64G IP has taped out on A14, adding a concrete interface-IP milestone to the node’s design ecosystem. - Analog Bits says its IP will be included in an upcoming customer test-chip tapeout on TSMC A14. - Siemens and TSMC are highlighting AI-assisted automated DRC fixing as a way to reduce manual design iterations and accelerate time to tapeout. - TrendForce reports that 2027 long-term agreement prices for 12-inch wafers could rise roughly 15–25% for epitaxial wafers and more than 40% for polished wafers. - The reported A14 pilot acceleration does not change TSMC’s recently stated 2030 start for High-NA EUV high-volume manufacturing. - No new ASML scanner shipment count was disclosed this week; the strongest EUV signals came from A14 readiness and upstream wafer supply. Glossary Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light for the most demanding patterning layers in advanced logic and memory. High Numerical Aperture (High-NA) EUV — ASML’s next-generation EUV platform with higher numerical aperture for tighter single-exposure patterning. A14 — TSMC’s advanced logic process generation scheduled for volume production in 2028. Electronic Design Automation (EDA) — Software tools used to design, verify, implement and sign off integrated circuits. Design Rule Check (DRC) — Verification that a chip layout complies with foundry manufacturing rules. Tapeout — The point at which a chip design is finalized for mask generation and fabrication. Long-Term Agreement (LTA) — A multi-period commercial contract used to secure supply, pricing or both. 300-millimeter wafer — The standard silicon substrate diameter used for most advanced semiconductor manufacturing.

  8. Sep 21

    [064] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. ASML’s next EUV challenge is increasingly industrial rather than optical: reported 2028 capacity could exceed 110 systems, while the company appears committed to scaling its existing laser-produced-plasma source architecture rather than switching to free-electron lasers. At the same time, SK hynix is evaluating U.S. front-end manufacturing options, TSMC’s 2-nanometer node is gaining multiple flagship-mobile customers, and CXMT says its newest DRAM platform has entered mass production without EUV. Key takeaways - Reuters says ASML is examining ways to produce more than 110 EUV systems in 2028, with assembly speed reportedly the main constraint. - JPMorgan’s ASML readout says EUV intensity per chip is rising and High-NA adoption begins in 2028, becoming more meaningful over the following decade. - SiliconReport, citing JPMorgan, says ASML is unlikely to pursue a Free-Electron Laser source and is instead scaling laser-produced plasma toward roughly 1,000 watts. - SK hynix and Intel are discussing possible U.S. memory production involving Intel’s Ohio site, but SK hynix says no plan or partnership has been finalized. - Solidigm is separately considering a U.S. NAND factory, with upstate New York reported as a leading candidate; no investment decision has been made. - MediaTek’s Dimensity 9600 Pro uses TSMC’s 2-nanometer process, while Apple’s A20 Pro provides a second major flagship-mobile demand anchor for 2-nanometer production. - CXMT says its fifth-generation DRAM platform is in mass production using quadruple patterning, with 11.95-nanometer feature spacing and at least 50% more gross dies per wafer than its prior platform. - Micron and its Taiwan union completed a first mediation session without a reported production interruption; a second session is scheduled for October 22. - Unclear item: the product type, ownership structure, timing, and lithography requirements of any SK hynix-Intel U.S. memory project remain undisclosed. Glossary EUV — Extreme Ultraviolet lithography, the 13.5-nanometer exposure technology used for leading-edge semiconductor patterning. High-NA — High Numerical Aperture EUV, ASML’s higher-resolution EUV platform entering production selectively before broader adoption later in the decade. FEL — Free-Electron Laser, an accelerator-based light-source concept discussed as a possible alternative way to generate EUV radiation. DRAM — Dynamic Random-Access Memory, volatile working memory used in servers, PCs, smartphones, and accelerators. HBM — High Bandwidth Memory, stacked DRAM optimized for very high data throughput in AI and high-performance computing systems. NAND — Non-volatile flash memory used for persistent data storage. DUV — Deep Ultraviolet lithography, the established optical patterning platform that can be extended through multiple-patterning techniques. Gross dies per wafer — The theoretical number of dies patterned on a wafer before defective dies are removed from the count.

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About

EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast. Industry Briefings: Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co. Focus Deep Dives: Unpack physics, plasma, optics and how EUV scanners really work. Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites. AI can make mistakes: always verify the information independently before using it as a basis for business decisions.

Information

  • Creator
    EUV The Focal Point - Team
  • Years Active
    2025 - 2026
  • Episodes
    71
  • Rating
    Clean
  • Copyright
    © EUV The Focal Point - Team
  • Show Website
    EUV The Focal Point