Semi Doped

Vikram Sekar and Austin Lyons
  • 5.0 (22)
  • Technology

The business and technology of semiconductors. Alpha for engineers and investors alike.

  1. 2d ago

    RF Over Plastic Is a Third Option Between Copper and Optics: Point2's Sean Park

    A novel third option is emerging for data center interconnects between short-reach copper and power-hungry optics. Point2 CEO Sean Park joins Vik Sekar to explain his company's Active RF Cable (ARC) technology, which sends high-frequency radio signals over a flexible plastic waveguide. Park details how this approach targets the critical 5-10 meter "scale-up" problem for AI clusters, claiming significant advantages in cable density, power efficiency, and latency over existing solutions. This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe "The bandwidth limitation simply comes from the existence of electrons. And this plastic, it doesn't have electron. So, in terms of bandwidth, it is unlimited. Bandwidth is unlimited. So, once our silicon works, we don't have to really change the this cable at all. Just scale the silicon, then it will it will be used for higher data rate." — Sean Park, Point2 Technology Key Takeaways: - The interconnect choice is no longer just copper vs. optics. Point2's Active RF Cable (ARC) creates a third category, sending 100-200 GHz signals over a plastic waveguide for the 5-10 meter reach AI scale-up requires. - The core density advantage is 4x over copper. ARC uses a single plastic core instead of a differential pair (2x gain), then sends two channels per core using frequency division multiplexing (another 2x gain). - The power savings come from silicon simplicity. By avoiding the laser, DSP, and TIA of optical modules, a 1.6T ARC module consumes 10 watts (~5 pJ/bit), with a roadmap to 2 pJ/bit for co-packaged versions. - The latency improvement is three orders of magnitude. Because it requires no DSP, ARC latency is in the sub-nanosecond range — 1,000x better than DSP-based optical solutions, which is critical for all-reduce operations. - The cable itself has a clear scaling path that copper lacks. A plastic waveguide is a dielectric with theoretically unlimited bandwidth, free of the skin effect that limits copper. Future speed gains will come from silicon shrinks alone. - Practicality in the rack is a key feature. The flexible plastic cable has a 4.7 mm bend radius, tight enough to wrap around a finger, making it easier to route in dense chassis than fragile optical fiber. Chapters: 0:00 Intro: RF Over Plastic 3:06 The Third Option 8:27 Investor Validation 13:20 How E-Tube Works 15:16 The 4x Density Advantage 18:28 Inside the OSFP Module 29:51 4.7mm Bend Radius 34:20 Roadmap to Co-Packaging 36:09 The No-Gearbox Advantage 42:00 Biggest Challenges 49:57 The Physics of Scaling 51:00 Origin Story: Wallpaper TV Mentioned in this episode: - Plastic Cables for AI Clusters: Can Point2’s E-Tube Disrupt Copper and Optics? (Vik's Newsletter, paid): https://www.viksnewsletter.com/p/plastic-cables-for-ai-clusters-etube Follow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/chipstrat Follow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskr Follow Semi Doped: Get more of Austin and Vik daily, free: https://daily.semidoped.com/

  2. 5d ago

    MicroVCSELs vs MicroLEDs, a MicroExplainer

    Austin Lyons and Vik Sekar host a micro-explainer on the two competing micro-emitter technologies for AI interconnects: microLEDs and microVCSELs. They break down Credo's surprising pivot at OCP from its microLED acquisition to a microVCSEL product, revealing the core physics that give microVCSELs superior speed and reach. The episode establishes the technical reasons why the industry is converging on microVCSELs for the critical 5-50 meter gap in AI data centers. This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe Key Takeaways: - The new battleground for AI interconnects is the 5-50 meter "reach gap"—too long for copper cables limited to ~7 meters, but too short for expensive, supply-constrained InP long-reach optics. - MicroLEDs are limited by physics to ~3-5 Gbps over 5 meters. Their broad light spectrum causes "chromatic dispersion," smearing the signal and creating a hard ceiling on speed and reach. - To achieve high bandwidth, microLEDs require massive parallelism—bundling ~300 slow lanes to hit 1 Tbps—which introduces significant manufacturing complexity in coupling hundreds of fibers. - MicroVCSELs solve this, hitting 50 Gbps+ over 50 meters. Their "stimulated emission" physics creates a narrow, focused beam that suffers less from dispersion, enabling 10x the speed and reach of microLEDs. - The supply chain is a key advantage. MicroVCSELs use a mature Gallium Arsenide (GaAs) process on 8-inch wafers, shared with cell phones, giving them a cost and scale advantage over exotic InP optics. - MicroLEDs' niche is extreme heat. Their Gallium Nitride (GaN) material is highly temperature-insensitive, making them a candidate for very short-reach, high-reliability optics inside a hot server tray. Chapters: 0:00 The Credo Pivot 3:49 The Talk of OCP 8:13 The 5-50 Meter Reach Gap 12:52 How MicroLEDs Work 21:10 MicroLEDs' Parallelism Problem 22:55 How MicroVCSELs Work 26:57 MicroVCSEL Performance Specs 31:51 The Physics of VCSELs 33:35 The Market Chooses MicroVCSELs 35:45 MicroLEDs' Niche: Heat 38:16 Teasing Future Interviews Mentioned in this episode: - PicoJool’s Al Yuen: The Case for GaAs VCSELs in Scale-Up Interconnects (Semi Doped episode): https://daily.semidoped.com/p/picojools-al-yuen-the-case-for-gaas - A MicroLED Field Trip to Avicena (Vik's Newsletter, paid): https://www.viksnewsletter.com/p/a-microled-field-trip-to-avicena - MicroLEDs vs. Lasers: The Linewidth Tradeoff (Vik's Newsletter, free): https://www.viksnewsletter.com/p/microleds-vs-lasers-the-linewidth-tradeoff - Understanding Energy Bands in Semiconductors (Vik's Newsletter, free): https://www.viksnewsletter.com/p/energy-bands-in-semiconductors Follow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/chipstrat Follow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskr Follow Semi Doped: Get more of Austin and Vik daily, free: https://daily.semidoped.com/

  3. Oct 15

    AI Inference Is a Data Movement Problem: Microsoft's Saurabh Dighe on Maia 300

    Microsoft's Maia 300 is a fully co-designed system, optimized to solve the memory-bound "data movement problem" of emerging agentic AI workloads.  Saurabh Dighe, Corporate VP of Azure Hardware Systems at Microsoft, sits down with Austin to detail the architecture, from its TSMC N2P chiplet design enabling 18 TB/s of HBM4 memory bandwidth to its use of AI agents for automated kernel optimization.  They discuss how this full-stack approach aims to maximize intelligence per watt and per dollar for Microsoft's planet-scale services. This episode is presented by @CrusoeAI. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe Key Takeaways: - Microsoft views AI inference as a data movement problem, not a compute problem. The energy cost of moving data to feed the compute engine can be two orders of magnitude higher than the compute itself. - The design of Maia 300 is driven by the shift from chat to agentic AI, which creates memory-bound workloads. The system delivers a 7x token throughput increase per rack over Maia 200, with a 5x increase in rack-level memory bandwidth. - Maia 300 uses a chiplet architecture to "extend the shoreline" of its single TSMC N2P compute die. This allows it to accommodate eight HBM4 stacks, delivering 18 TB/s of memory bandwidth. - Microsoft is using AI agents for "agentic kernel optimization" to automate the creation of low-level software. This strategy aims to bypass the manual optimization bottleneck and enable "Day-zero model availability" for new AI models. - The system is built for deployment flexibility. While servers use direct liquid cooling, a rack-level "heat exchanger unit" allows the 167 kW racks to be deployed in traditional air-cooled data centers. - The network is a two-tiered scale-up fabric built on standard Ethernet. Copper connects the 96 accelerators within a rack, while optics connect racks into superpods of up to 12,288 accelerators. Chapters: 0:00 Intro: Saurabh Dighe 1:39 Microsoft's Silicon Philosophy 5:52 Workload Shift: Agentic AI 9:32 The Data Movement Problem 14:20 Crusoe Ad Read 17:47 Maia 300 Specs 24:07 Chiplets & HBM4 29:12 Prefill/Decode Disaggregation 30:33 Two-Tiered Network 35:45 NPO vs. CPO 36:46 Rack-Scale Power & Cooling 41:35 Agentic Kernel Optimization 49:08 What's Next: Maia 400 Follow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/chipstrat Follow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskr Follow Semi Doped: Get more of Austin and Vik daily, free: https://daily.semidoped.com/

  4. Oct 8

    Synopsys’s Amazon Deal and GPT-Synopsys: Ravi Subramanian

    The demand for workload-specific hardware is forcing a strategic shift in the semiconductor IP business. Synopsys's Ravi Subramanian joins Austin to discuss why the company is moving to a new royalty-based model for its custom "application optimized IP," starting with a billion-dollar deal with Amazon. Ravi also unpacks Synopsys's partnership with OpenAI and its vision for AI "agent engineers" that augment human designers, while explaining why physics-based simulation remains the ultimate ground truth. This episode is presented by Crusoe. Try Crusoe's managed inference for open models with $5 in free credits: https://semidoped.com/crusoe "in physics we trust is because at the end of the day, the ground truth to have the confidence, not hallucinate and be deterministic in your outcome is really what defines is a product going to be successful or not." — Ravi Subramanian, Synopsys Key Takeaways: - The hyperscaler IP model is shifting. Because 1-2 applications drive most revenue, companies like Amazon now demand custom “application optimized IP” instead of standards-based IP. - Synopsys is adopting a new business model for this custom work: a license fee, a “customization fee” to prioritize scarce engineers, and for the first time, a royalty on the final chip. - This new royalty model mirrors the Arm-Amazon partnership from a decade ago, aligning Synopsys with its customer’s 12-month design cycles and expanding its role to system-level bring-up. - Synopsys’s AI strategy isn't just tools, but a new consumption model: customers can “hire” an AI agent engineer with a specific skillset, fitting directly into existing budgets and team structures. - The GPT-Synopsys partnership with OpenAI is a turnkey service bundling a specialized LLM, the necessary compute, and forward-deployed engineers to solve the key adoption hurdles of model quality and compute scarcity. - AI is for exploration, but physics is for verification. Accurately modeling a modern CFET requires 200x more device equations than a planar FET, a complexity that demands physics-based simulators as the ground truth. Chapters: 0:00 Intro: The Amazon & OpenAI Deals 2:39 Application Optimized IP 6:04 The New Royalty Business Model 12:14 How Standard IP Differentiates 18:20 The Arm-Amazon Analogy 22:00 Synopsys's Role in Test Chips 26:06 The Three Stages of Chip Design 31:27 The 'Agent Engineer' AI Model 36:20 The GPT-Synopsys Partnership 39:27 In AI We Believe, In Physics We Trust Follow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/chipstrat Follow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskr Follow Semi Doped: Get more of Austin and Vik daily, free: https://daily.semidoped.com/

  5. Oct 1

    Every Muse User Gets 2 CPUs and 8GB in Meta's Cloud. Your Phone Already Has That

    The push to run AI agents on edge devices will not be driven by model labs or hardware vendors, but by service providers like Meta whose ad-based business models create a powerful financial incentive to offload massive cloud compute costs onto the user's own powerful-but-idle hardware. Austin Lyons and Vik Sekar break down why the failed "AI PC" push has given way to a new, economically-driven strategy for on-device AI. They discuss how Qualcomm's acquisition of Modular provides the key software layer and why the ultimate vision is an "ecosystem of you" where the device acts as a context-aware orchestrator between local and cloud compute. This episode is presented by Crusoe. Try Crusoe's managed inference for open models with $5 in free credits: https://semidoped.com/crusoe "[Model Labs] business model is we make money when we do inference in the cloud. And yet we are saying, actually, there's a world where we would really like to just run this stuff locally... Meta's like, bro, I want to help you at the edge." — Austin Lyons, Chipstrat Key Takeaways: - The driver for edge AI is a business model conflict. Model labs like OpenAI sell cloud inference; service providers like Meta see it as a massive cost center for their ad-supported agents like Muse. - Your phone is an underutilized edge server. Its specs—like 8GB of RAM and 2 vCPUs of power—are comparable to the dedicated cloud VMs that services like Meta's Muse provision for each user. - The "AIPC" push failed because it was a hardware-first strategy without a use case. Today's edge AI push is a software-first strategy driven by the need to cut cloud OpEx for mass-market agents. - The role of the edge device is becoming a "context translation layer." It uses private data like location and biometrics to intelligently decide which AI tasks run locally versus in the cloud. - Qualcomm's acquisition of Modular is a key strategic move. It positions the open-source Mojo language as the "write once, run anywhere" software layer for deploying agents across diverse hardware. - Personal agents will lead to the "end of apps." Fixed UIs, which force a designer's paradigm on the user, will be replaced by interfaces generated on demand via natural language. - Google is missing its opportunity to lead in on-device AI. Despite vertical integration from TPUs to Pixel hardware and a leading ad business, it lacks the product execution of players like Meta. Chapters: 0:00 Who Makes Local AI Happen? 1:25 Making the Intro with AI 4:43 Qualcomm's Agent Vision 6:54 Why AIPCs Failed 8:45 The Phone as a Portal 13:52 Meta's Incentive for Edge AI 24:05 The End of Apps & UIs? 32:31 The Ideal Personal Agent 34:25 The Edge as a Context Layer 38:17 Qualcomm's Modular Acquisition 43:16 The Ecosystem of You 48:01 Google's Missed Opportunity Follow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/chipstrat Follow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskr Follow Semi Doped: Get more of Austin and Vik daily, free: https://daily.semidoped.com/

  6. Sep 29

    Flash Hit Its Physical Limit. ReRAM Is the Replacement: WeeBit Nano's Ilan Sever

    As embedded flash hits a physical and economic scaling wall below 22nm, a new on-chip memory is needed. Ilan Sever of WeeBit Nano joins to explain how Resistive RAM (ReRAM) is positioned to become the new standard by offering a low-cost, high-endurance alternative. Ilan details how ReRAM's simple back-end-of-line integration, automotive qualification, and future applications in AI in-memory compute create a compelling replacement for the incumbent technology. "In geometries below 28 or 22 nanometer, flash reached its physical limit, actually. So physically you cannot implement embedded flash anymore and the industry had been looking for alternative technologies for a few decades now." — Ilan Sever, WeeBit Nano Key Takeaways: - The inflection point for on-chip memory is physical. Embedded flash cannot scale below the 28/22nm node because its floating gate becomes too small to reliably hold charge. - The economic problem with eFlash is its 25-30% cost increase, a result of adding 8-10 extra masks to a standard CMOS process—a non-starter for cost-sensitive MCUs. - ReRAM's manufacturing advantage is its simplicity. It's built in the back-end-of-line (BEOL) metal layers, adding only two masks and not interfering with the sensitive transistors below. - The physics are different: ReRAM isn't storing charge, it's changing resistance by using voltage to form or dissolve a conductive filament of oxygen vacancies in a dielectric. - Automotive qualification is the key market validation. WeeBit's ReRAM is qualified for the AEC-Q100 standard and demonstrates 100,000 write cycles—10x that of typical eFlash. - The business model isn't just a recipe; it's a full IP module with the bit cell, analog circuits, digital logic, and programming algorithms, which is what SoC designers actually need. - Beyond replacing flash, ReRAM (as a memristor) is a foundational technology for future in-memory compute (IMC) AI accelerators that perform calculations inside the memory to save power. Chapters: 0:00 The Overlooked Memory 4:15 The eFlash Scaling Wall 6:03 Four Uses of NVM 23:19 The Cost of eFlash 27:29 Introducing ReRAM 32:25 How ReRAM Works 37:12 Fab-Friendly Materials 42:14 Automotive Qualification 44:30 The Vertically Integrated IP Model 51:13 Future: In-Memory Compute 54:19 Innovation Story: Self-Trimming Follow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/chipstrat Follow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskr Follow Semi Doped: Get more of Austin and Vik daily, free: https://daily.semidoped.com/

  7. Sep 24

    Qualcomm's Durga Malladi: HBC vs HBM, Dragonfly AI 250, and Winning on TCO

    Qualcomm re-entered the data center inference market late — competitive GPUs, XPUs, and custom accelerators are already out there. Durga Malladi (EVP/GM, Technology Planning, Edge & Data Center) explains why they didn't build another me-too accelerator and instead placed a differentiating technical bet: High Bandwidth Compute (HBC). The difference between HBC and HBM: HBM is stacked DRAM that shuttles data across wide buses to a separate accelerator — very high bandwidth, but expensive and power-hungry. HBC bonds stacked DRAM directly on top of a custom logic die using wafer-on-wafer techniques, so a lot of the compute runs literally next to memory. The result is lower latency and lower power per bit — and 18x effective bandwidth on the AI 250 versus the AI 200 at the SAME 768 GB LPDDR capacity and the SAME 160 kW per rack. Why the late-mover bet works: Qualcomm's differentiation isn't just architectural. Their foundry and memory-vendor relationships let them credibly promise the multi-megawatt-to-gigawatt supply hyperscalers need. Memory vendors are developing their own HBC-equivalent variants as partners rather than pure competitors, and Qualcomm expects the two technologies to co-evolve. Silicon is back in the lab; proof points land in Q1/Q2 2027. Chapters: 0:00 Introduction 2:49 The Memory Wall Problem 8:05 HBC Physical Architecture 9:33 HBC vs. Custom HBM 11:50 Silicon Proof Points Coming 12:08 Managing Thermals 13:34 Dragonfly AI 250 14:48 Trillion-Parameter Model on One Card 16:56 Tokenomics and TCO 18:26 Why TCO is Key 19:26 Manufacturing at Scale Follow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/chipstrat Follow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskr Follow Semi Doped: Get more of Austin and Vik daily, free: https://daily.semidoped.com/

  8. Sep 18

    Pacing AI Means More Compute, Not Less

    The debate over "pacing" AI for safety is a red herring, as the practical outcome of more safety work is not a slowdown but a net increase in demand for compute hardware. Austin Lyons and Vik Sekar unpack Dario Amodei's call to slow down frontier AI development, arguing that the true governors on AI are not voluntary agreements but physical data center bottlenecks and geopolitical realities. They conclude that the push for more safety and interpretability will ultimately drive more sales of both training (GPUs) and inference (XPUs) hardware. Today's sponsor is G2i — expert training data, evals, and RL environments for AI labs: https://fandf.co/4wZvKHS Chapters: 0:00 Introduction: Pacing AI 1:36 Recapping Dario Amodei's Essay 7:42 Hot Take: Anthropic vs. OpenAI 11:34 The John Deere Playbook 15:22 The Problem with Interpretability 17:53 Pulling the Plug 19:03 The Real Bottleneck: Data Centers 22:03 The Geopolitical Blind Spot 23:41 Counter-narratives: Meta & Open Source 27:26 The Investment Thesis: Pacing Increases Compute 32:29 The Financial System Analogy 36:05 AI Safety as the New Cybersecurity Follow Chipstrat: Newsletter: https://www.chipstrat.com X: https://x.com/chipstrat Follow Vik: Newsletter: https://www.viksnewsletter.com/ X: https://x.com/vikramskr Follow Semi Doped: Get more of Austin and Vik daily, free: https://daily.semidoped.com/

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Ratings & Reviews

5
out of 5
22 Ratings

About

The business and technology of semiconductors. Alpha for engineers and investors alike.

Information

  • Creator
    Vikram Sekar and Austin Lyons
  • Years Active
    2026
  • Episodes
    54
  • Rating
    Clean
  • Copyright
    © 2026 Semi Doped
  • Show Website
    Semi Doped

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