InvasIC Seminar: Vorträge im SFB/TRR 89

Prof. Dr. Jürgen Teich
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http://invasic.de

  1. Episode 1 ·  Video

    Kernfragen: Multicore-Prozessoren in der Industrie

    Urs Gleim, Leiter des Parallel Processing Systems Teams bei der zentralen Forschung der Siemens AG (Corporate Technology), diskutiert in diesem Vortrag die technischen Herausforderungen der nächsten Jahre aus industrieller Sicht. Der Schwerpunkt der Betrachtung liegt auf der Nutzung neuer, insbesondere paralleler, Hardwarearchitekturen. Abschließend stellt er ausgewählte aktuelle Arbeiten der Siemens Corporate Technology in diesem Umfeld vor.

  2. Episode 2 ·  Video

    Efficiency Metrics and Bandwidth – A Memory Perspective

    The race for increasing computing performance implied a dramatic increase in power which represents the main wall for further increase in computing. The “multi-core revolution” has shown a way out. Thus, today’s state-of-the-art architectures in embedded computing are based on heterogeneous multi-core architectures with application specific optimized accelerators. Unfortunately the immense computing power of such multi-core architectures brings as negative effect an increased demand on bandwidth and memory, denoted as bandwidth and memory walls. In this talk we will discuss two topics strongly related to the memory and bandwidth wall. First, the impact of memories and data transfers on metrics to compare different algorithms and implementations in the context of wireless baseband processing architectures. Second, the design space and potential of 3D DRAM architectures and multi-channel DRAM controllers.

  3. Episode 3 ·  Video

    Kernel Offloading for FPGA with Optimized Remote Accesses

    Some data- and compute-intensive applications can be accelerated by offloading portions of codes to platforms such as GPGPUs or FPGAs. However, to get high performance for these kernels, it is mandatory to restructure the application, to generate adequate communication mechanisms for the transfer of remote data, and to make good usage of the memory bandwidth. In the context of the high-level synthesis (HLS), from a C program, of hardware accelerators on FPGA, we show how to automatically generate optimized remote accesses for an accelerator communicating to an external DDR memory. Loop tiling is used to enable block communications, suitable for DDR memories. Pipelined communication processes are generated to overlap communications and computations, thereby hiding some latencies, in a way similar to double buffering. Finally, data reuse among tiles is exploited to avoid remote accesses when data are already available in the local memory.

  4. Episode 4 ·  Video

    HOPES: A Model-Based Design Framework of Parallel Embedded Systems

    HOPES: A Model-Based Design Framework of Parallel Embedded Systems

  5. Episode 5 ·  Video

    Robust System Design

    Robust System Design

  6. Episode 6 ·  Video

    Programmability and Performance Portability for Heterogeneous Many-Core Systems

    Programmability and Performance Portability for Heterogeneous Many-Core Systems

  7. Episode 7 ·  Video

    When does it get hot?

    With the evolution of today´s semiconductor technology, chip temperature increases rapidly mainly due to the growth in power density. However, the obtained increase in performance imposes a major increase in temperature, which in turn reduces the system reliability. Exceeding a certain threshold temperature could lead to a reduction of performance, or even the damage of the physical system. The presentation will describe models and methods that link the discrete world of computations with temperature. This allows to answer some fundamental questions like: What is the maximal temperature during a computation? What timing properties can be guaranteed under feedback control of temperatures? In addition, we will show how the temperature constraint can be integrated into a high-level programming environment for embedded multiprocessor systems.

  8. Episode 8 ·  Video

    Organic Computing - Quo vadis?

    Organic Computing - Quo vadis?

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