EUV The Focal Point

EUV The Focal Point - Team

EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast. Industry Briefings: Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co. Focus Deep Dives: Unpack physics, plasma, optics and how EUV scanners really work. Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites. AI can make mistakes: always verify the information independently before using it as a basis for business decisions.

  1. 1d ago

    [067] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. New TSMC and Samsung figures reinforce the scale of semiconductor demand, while GlobalFoundries adds a dated interposer-supply plan for TSMC. The focus examines the Hyper-NA study's principal unresolved constraint: a smaller focus budget and the need for thinner resists. Architectural reuse could limit transition spending, but the proposed optics are not a commercial production commitment. Key takeaways - TSMC reported September revenue of NT$511.86 billion, up 54.6% year on year and down 0.6% month on month; January–September revenue grew 41.1%. - Samsung's preliminary Q3 guidance projects KRW195 trillion in consolidated sales and KRW107.4 trillion in operating profit, versus KRW12.17 trillion profit a year earlier; these are estimates, not final or foundry-specific results. - SIA reported sales exceeding US$1 trillion through August; its August figure of US$159.7 billion, up 8% sequentially, uses a WSTS three-month moving average. - Reuters reported AMD's plan for a substantial 2027 supply increase and need for more advanced wafer capacity; no wafer-volume, node-allocation or new-fab commitment was disclosed in those comments. - GlobalFoundries announced a US$2 billion agreement with TSMC for CoWoS silicon interposers, an initial five-year term and an expected Malta, New York volume ramp in H1 2028; this is packaging-component capacity. - The October 1 Hyper-NA paper proposes at least 0.75 numerical aperture at 13.5 nm and approximately 5 nm optical half-pitch; its roughly ten-year development estimate is not a committed delivery date. - The study identifies an approximately halved idealized depth of focus versus 0.55 NA, motivating better focus control and thinner resists; actual process windows remain pattern-dependent. - Source reuse leaves future power needs open; polarization can improve contrast but introduces a photon penalty, and a proposed 0.75-NA micro-exposure tool could support resist development. - ASML and TSMC have Q3 results scheduled for October 14 and 15 respectively; watch output guidance, advanced-node capacity and packaging execution, alongside measured Hyper-NA resist/focus results. Glossary EUV — Extreme ultraviolet lithography; the proposal retains the 13.5 nm wavelength. High-NA — High numerical aperture EUV; the 0.55-NA platform used as the study's comparison. Hyper-NA — Proposed EUV architecture with numerical aperture of at least 0.75. Half-pitch — Half the repeat distance of a periodic pattern; distinct from a commercial node name. Depth of focus — Axial imaging tolerance; an idealized optical value is not a complete manufacturing process window. Resist — Photosensitive patterning film; thinning it changes photon absorption and pattern-transfer requirements. Edge-placement error — Difference between an intended pattern edge and its realized position. Micro-exposure tool — Small-field research exposure system for developing materials under future optical conditions. CoWoS — Chip on Wafer on Substrate, TSMC's advanced packaging platform.

  2. Oct 5

    [066] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Micron's September 30 results provide a concrete follow-up to last week's investment outlook, while Samsung projects a larger share of DRAM wafer capacity going to HBM. This episode examines how take-or-pay commitments improve investment visibility and why product mix, qualification and delivery timing still determine the EUV implications. Key takeaways - Micron reported fiscal Q4 2026 revenue of $54.23 billion and full-year net capital expenditure of $27.37 billion; financial growth is not a physical capacity measure. - Micron guides approximately $25 billion of net capex for the first half of fiscal 2027, with higher spending in the second half; $25 billion is not its full-year budget. - Samsung's Kim Taewoo expects HBM to use nearly 30% of industry DRAM wafer capacity in 2027, versus about 20% currently; this is an expectation, not market share or bit share. - Micron reports 26 multi-year take-or-pay SCAs, estimated to cover over 35% of revenue through 2030, with some agreements extending into 2031. - Micron identifies 1-gamma as its largest DRAM production node; its technology documentation confirms EUV use. - Micron says Singapore HBM packaging cleanroom preparation is ahead of plan, with initial output expected in early calendar 2027; packaging is distinct from front-end wafer capacity. - The September 28 outlook is partly answered on spending; a precise Micron HBM4E production date remains unestablished in the sources used here. - Analysis: translating contracted bits into exposure demand requires product mix, bits per wafer, yield and patterning-flow assumptions. - Fresh qualifying news was concentrated in memory; already-covered A14 pilot and silicon-wafer pricing reports were excluded from the news segment. Glossary EUV — Extreme ultraviolet lithography, used to pattern selected critical semiconductor layers. HBM — High Bandwidth Memory, a stacked DRAM product designed for high data bandwidth. DRAM — Dynamic Random-Access Memory, volatile memory used in computing systems. SCA — Strategic Customer Agreement; Micron uses this term for its multi-year customer supply arrangements. Take-or-pay — A contractual obligation to take an agreed quantity or make the required payment, subject to the agreement's terms. Net capex — Capital expenditure after the relevant offsets; Micron's guidance is net of anticipated government incentives. 1-gamma — Micron's EUV-enabled DRAM technology generation, also written 1γ. Front-end capacity — Wafer fabrication capacity, distinct from subsequent packaging and assembly. Qualification — Validation that a product or manufacturing process meets the relevant requirements before broader deployment.

  3. Sep 28

    [065] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. TSMC’s A14 program is becoming more operational: reported pilot timing is moving earlier while the design ecosystem is filling in with certified flows, interface IP and customer test-chip activity. At the same time, reported 300-millimeter wafer price pressure shows that AI-driven scarcity is moving deeper into the manufacturing supply chain. The EUV implication is important: more near-term pressure on the established EUV fleet does not mean TSMC is bringing High-NA production forward. Key takeaways - TrendForce reports that TSMC could begin A14 pilot production at Baoshan in 1Q27, while the company’s volume-production target remains 2028. - Cadence and Synopsys announced certified EDA flows for TSMC A14 at the 2026 North America OIP Ecosystem Forum. - Cadence says UCIe-64G IP has taped out on A14, adding a concrete interface-IP milestone to the node’s design ecosystem. - Analog Bits says its IP will be included in an upcoming customer test-chip tapeout on TSMC A14. - Siemens and TSMC are highlighting AI-assisted automated DRC fixing as a way to reduce manual design iterations and accelerate time to tapeout. - TrendForce reports that 2027 long-term agreement prices for 12-inch wafers could rise roughly 15–25% for epitaxial wafers and more than 40% for polished wafers. - The reported A14 pilot acceleration does not change TSMC’s recently stated 2030 start for High-NA EUV high-volume manufacturing. - No new ASML scanner shipment count was disclosed this week; the strongest EUV signals came from A14 readiness and upstream wafer supply. Glossary Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light for the most demanding patterning layers in advanced logic and memory. High Numerical Aperture (High-NA) EUV — ASML’s next-generation EUV platform with higher numerical aperture for tighter single-exposure patterning. A14 — TSMC’s advanced logic process generation scheduled for volume production in 2028. Electronic Design Automation (EDA) — Software tools used to design, verify, implement and sign off integrated circuits. Design Rule Check (DRC) — Verification that a chip layout complies with foundry manufacturing rules. Tapeout — The point at which a chip design is finalized for mask generation and fabrication. Long-Term Agreement (LTA) — A multi-period commercial contract used to secure supply, pricing or both. 300-millimeter wafer — The standard silicon substrate diameter used for most advanced semiconductor manufacturing.

  4. Sep 21

    [064] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. ASML’s next EUV challenge is increasingly industrial rather than optical: reported 2028 capacity could exceed 110 systems, while the company appears committed to scaling its existing laser-produced-plasma source architecture rather than switching to free-electron lasers. At the same time, SK hynix is evaluating U.S. front-end manufacturing options, TSMC’s 2-nanometer node is gaining multiple flagship-mobile customers, and CXMT says its newest DRAM platform has entered mass production without EUV. Key takeaways - Reuters says ASML is examining ways to produce more than 110 EUV systems in 2028, with assembly speed reportedly the main constraint. - JPMorgan’s ASML readout says EUV intensity per chip is rising and High-NA adoption begins in 2028, becoming more meaningful over the following decade. - SiliconReport, citing JPMorgan, says ASML is unlikely to pursue a Free-Electron Laser source and is instead scaling laser-produced plasma toward roughly 1,000 watts. - SK hynix and Intel are discussing possible U.S. memory production involving Intel’s Ohio site, but SK hynix says no plan or partnership has been finalized. - Solidigm is separately considering a U.S. NAND factory, with upstate New York reported as a leading candidate; no investment decision has been made. - MediaTek’s Dimensity 9600 Pro uses TSMC’s 2-nanometer process, while Apple’s A20 Pro provides a second major flagship-mobile demand anchor for 2-nanometer production. - CXMT says its fifth-generation DRAM platform is in mass production using quadruple patterning, with 11.95-nanometer feature spacing and at least 50% more gross dies per wafer than its prior platform. - Micron and its Taiwan union completed a first mediation session without a reported production interruption; a second session is scheduled for October 22. - Unclear item: the product type, ownership structure, timing, and lithography requirements of any SK hynix-Intel U.S. memory project remain undisclosed. Glossary EUV — Extreme Ultraviolet lithography, the 13.5-nanometer exposure technology used for leading-edge semiconductor patterning. High-NA — High Numerical Aperture EUV, ASML’s higher-resolution EUV platform entering production selectively before broader adoption later in the decade. FEL — Free-Electron Laser, an accelerator-based light-source concept discussed as a possible alternative way to generate EUV radiation. DRAM — Dynamic Random-Access Memory, volatile working memory used in servers, PCs, smartphones, and accelerators. HBM — High Bandwidth Memory, stacked DRAM optimized for very high data throughput in AI and high-performance computing systems. NAND — Non-volatile flash memory used for persistent data storage. DUV — Deep Ultraviolet lithography, the established optical patterning platform that can be extended through multiple-patterning techniques. Gross dies per wafer — The theoretical number of dies patterned on a wafer before defective dies are removed from the count.

  5. Sep 14

    [063] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. High-NA EUV adoption now has clearer dates: TSMC says it intends to enter high-volume manufacturing in 2030, while Samsung targets advanced DRAM production in 2028. Intel’s new million-wafer disclosure and imec’s chemically amplified resist results show that the next phase is increasingly about reducing ecosystem cost and integration risk rather than proving the scanner can print. Key takeaways: - TSMC intends to use High-NA EUV in high-volume manufacturing for advanced nodes starting in 2030. - ASML and TSMC target a 12-inch photomask pilot line by 2031 and a path to advanced-node production readiness by 2033. - Samsung plans to introduce High-NA EUV into future DRAM high-volume manufacturing by 2028 and will join the 12-inch mask initiative. - Reuters reports that SK hynix also plans High-NA production from 2028, while Micron has ordered systems but has not disclosed a production date. - Intel Foundry and ASML say more than one million wafers have now been processed with High-NA across certification, R&D and selected Panther Lake volume-production layers. - Imec demonstrated CAR-based High-NA single patterning down to 22nm-pitch lines and 28nm center-to-center vias for logic-relevant structures. - The imec result suggests established chemically amplified resist technology can remain useful for several critical A14/A10-class layers, reducing early integration burden. - Samsung and SK hynix rejected a proposed 25 trillion won upfront payment to finance power infrastructure for planned Korean semiconductor mega-clusters, leaving an important capacity-enablement question unresolved. Glossary: Extreme Ultraviolet (EUV) lithography — Lithography using 13.5nm-wavelength light for advanced semiconductor patterning. High Numerical Aperture (High-NA) EUV — ASML’s next-generation EUV platform using higher numerical aperture for finer patterning. Chemically amplified resist (CAR) — A mature photoresist platform in which exposure triggers chemistry that amplifies the imaging reaction. High-volume manufacturing (HVM) — Stable, sustained production at commercial fab scale. Photomask — The patterned optical template used to transfer circuit features during lithography. Stitching — Combining adjacent exposure fields to create a pattern larger than a single High-NA exposure field. Dynamic Random-Access Memory (DRAM) — Volatile memory technology used in computing systems and High Bandwidth Memory products. NXE platform — ASML’s established 0.33 numerical-aperture EUV scanner family. A14/A10 — Advanced logic technology generations in imec’s roadmap associated with ångström-class scaling.

  6. Sep 7

    [062] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. TSMC says its estimated equipment requirement for 2026 has risen to about 1.9 times the level projected at the end of 2025, showing how quickly AI demand is propagating into fab investment. This week also brings fresh signals from ASML’s Japan support expansion, semiconductor-material capacity in Taiwan, Micron labor risk, and the continuing gap between China’s DUV and EUV capabilities. Key takeaways - TSMC says its estimated 2026 semiconductor-equipment requirement reached about 1.9 times its end-2025 baseline by July. - TSMC is simultaneously building 13 fabs in Taiwan and another five or six overseas, yet says it still cannot fully meet customer demand. - ASML Japan reportedly plans to grow from roughly 500 employees to around 700 by 2030 as it supports Rapidus and other Japanese customers. - ASML’s Hokkaido engineering presence supporting Rapidus has reportedly increased from 24 people to about 50. - Solvay plans to more than double ultra-pure hydrogen peroxide capacity in Taiwan from 35,000 to more than 70,000 tonnes per year by the end of 2026. - Micron unions representing about 10,000 workers in Taiwan are threatening strike action over bonuses; more than 80% backed strike action in an August survey. - ZEISS semiconductor chief Frank Rohmund said roughly 15 years is a reasonable assumption for China to develop cutting-edge EUV, while stressing that progress is difficult to measure externally. - UBS analysts reportedly estimate that Chinese immersion DUV systems could reach high-volume manufacturing within roughly two to five years. - Last week’s outlook on whether AI demand would translate into stronger upstream commitments now has a concrete TSMC datapoint: equipment requirements have nearly doubled versus the year-end planning baseline. Glossary Extreme Ultraviolet (EUV) — Lithography technology used for the most advanced logic and memory patterning. Deep Ultraviolet (DUV) — Earlier-generation optical lithography technology that remains essential across advanced and mature semiconductor manufacturing. High-volume manufacturing (HVM) — Stable, repeatable production at commercial wafer volumes rather than laboratory or pilot operation. Dynamic Random-Access Memory (DRAM) — Volatile memory technology used in servers, PCs, mobile devices, and High Bandwidth Memory stacks. High Bandwidth Memory (HBM) — Vertically stacked DRAM optimized for very high bandwidth in AI and high-performance computing systems. Fab — A semiconductor fabrication facility where wafers are processed. Field service — On-site installation, maintenance, repair, calibration, and operational support for semiconductor equipment. Ultra-pure hydrogen peroxide — High-purity process chemical widely used in semiconductor wafer cleaning. Equipment requirement — The quantity and mix of manufacturing tools a chipmaker estimates it needs to support planned wafer capacity.

  7. Sep 3

    [061] Deep Dive Topic - Beyond Watts: What Really Determines Productive EUV Output

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Beyond Watts: What Really Determines Productive EUV Output EPISODE TEASER EUV lithography used to be dominated by one question: can the source generate enough 13.5-nanometer light for economical wafer throughput? In 2026, that is no longer the whole optimization problem. This episode explains why real fab value increasingly depends on productive output: throughput combined with availability, stability, maintainability, and cost per qualified wafer. KEY TAKEAWAYS - Source power remains a critical EUV enabler, but it is no longer a sufficient proxy for fab productivity. - Modern EUV throughput is a system property involving the source, wafer handling, precision stages, controls, metrology overhead, and process dose. - Nominal wafers per hour is condition-dependent; published low-NA throughput specifications are tied to a stated exposure dose. - Availability determines how often nominal scanner speed can actually be converted into fab capacity. - Power scaling must preserve source stability, collector lifetime, cleanliness, and serviceability to create production value. - Recent NXE:3800E gains came from a combination of higher source power, faster mechanics, improved handling, and software-based productivity upgrades. - Installed-base upgrades matter because fabs must extract more output from tools already in production, not only from newly purchased scanners. - The most useful economic endpoint is cost per qualified wafer, not maximum watts in isolation. - High-NA EUV reinforces the same lesson: imaging capability must mature together with throughput, availability, masks, resists, metrology, and service. GLOSSARY EUV lithography — Extreme ultraviolet lithography, a chip-patterning technology using light near 13.5 nanometers for leading-edge semiconductor manufacturing. Source power — The usable EUV optical power delivered by the light-source system; an important contributor to exposure speed. LPP — Laser-produced plasma, the EUV source method in which laser pulses strike tin droplets to create EUV-emitting plasma. Collector mirror — A multilayer mirror near the plasma source that gathers EUV radiation and directs it into the scanner. WPH — Wafers per hour, a scanner throughput metric measured under defined operating conditions. Availability — The share of scheduled production time during which a tool is capable of running production. Stability — The ability of the source and scanner to keep critical operating variables within the process window over time. Maintainability — How efficiently and predictably a system can be serviced and returned to production. Installed base — The population of lithography systems already operating at customer sites. Cost per wafer — The manufacturing cost allocated to each processed wafer, influenced by capital cost, throughput, uptime, service, energy, consumables, and yield-related performance.

    [061] Deep Dive Topic - Beyond Watts: What Really Determines Productive EUV Output

  8. Aug 31

    [060] Industry briefing - EUV The Focal Point

    This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week is light on new EUV scanner announcements but rich in semiconductor economics. NVIDIA’s demand, SK hynix’s U.S. HBM investment, Hot Chips memory disclosures, and Intel’s 18A-P versus possible TSMC sourcing choices show how utilization, wafer intensity, packaging, and capital allocation are becoming the decisive variables around advanced lithography. Key takeaways - NVIDIA reported Q2 FY2027 revenue of $96.2 billion and Data Center revenue of $89.0 billion, with Q3 revenue guided to $108.0 billion ±2%. - SK hynix broke ground on a more-than-$4-billion HBM packaging facility in Indiana; cleanroom opening is targeted for October 2028 and mass production for H2 2029. - The Indiana site will package and test advanced wafers made in South Korea, regionalizing the back end without duplicating the full EUV-intensive front-end flow in the U.S. - Micron said at Hot Chips that HBM requires roughly three times the wafer area of DDR5 for the same memory capacity, and that the ratio is not improving. - SK hynix indicated at Hot Chips that hybrid bonding is unlikely for HBM4E and may arrive with HBM5 at the earliest, extending the economic life of its current packaging approach. - Intel said Diamond Rapids uses Intel 18A-P, giving its leading-edge manufacturing platform additional internal volume. - TrendForce reported that Intel may consider TSMC N2X for some Razor Lake compute dies in 2027 depending on 18A-P performance; this remains unconfirmed. - Intel’s recent $20 billion equity offering and its Q2 Intel Foundry operating loss of about $2.1 billion underline why utilization and cost per good die matter as much as process milestones. - A useful follow-up to last week’s outlook arrived from SK hynix: a concrete capacity date is now available for Indiana, although not yet for the front-end M15X question. Glossary Extreme Ultraviolet (EUV) — Leading-edge lithography using 13.5-nanometer light for advanced logic and memory patterning. High Numerical Aperture (High-NA) EUV — ASML’s higher-resolution EUV platform used selectively by Intel in production learning. High Bandwidth Memory (HBM) — Stacked memory optimized for very high bandwidth in AI and high-performance computing systems. Dynamic Random-Access Memory (DRAM) — Volatile semiconductor memory; HBM is built from specialized DRAM dies. 18A-P — Intel’s performance-enhanced version of the Intel 18A process family. N2X — TSMC’s performance-oriented member of its 2-nanometer process family, targeted for 2027. Process Design Kit (PDK) — Foundry-provided design rules, models, and collateral used to build chips for a process. Hybrid bonding — Fine-pitch direct bonding approach intended to improve density and interconnect performance in advanced packages. Cost per good die — Manufacturing cost divided by the number of functional dies produced, combining yield, cycle time, and capital utilization.

See All (67)

About

EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast. Industry Briefings: Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co. Focus Deep Dives: Unpack physics, plasma, optics and how EUV scanners really work. Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites. AI can make mistakes: always verify the information independently before using it as a basis for business decisions.

Information

  • Creator
    EUV The Focal Point - Team
  • Years Active
    2025 - 2026
  • Episodes
    67
  • Rating
    Clean
  • Copyright
    © EUV The Focal Point - Team
  • Show Website
    EUV The Focal Point

You Might Also Like