Microarch Club

Dan Mangum
Microarch Club

The art, science, and history of processor design.

Episodes

  1. 02/28/2024

    10: Thomas Sohmers

    Thomas Sohmers joins to discuss dropping out of high school at age 17 to start a chip company, lessons from the successes and failures of past processor architectures, the history of VLIW, and the new AI hardware appliances he and his team are building at Positron AI. Thomas on X: https://twitter.com/trsohmers Thomas' Site: https://www.trsohmers.com/ Show Notes Welcome Thomas Sohmers (00:01:22)Growing Up Around Computers (00:03:13)Digging Beneath the Software (00:05:56)Learning Python, C, and Arduino C (00:07:05) https://www.arduino.cc/reference/en/Learning About the Thiel Fellowship (00:07:44) https://thielfellowship.org/Starting Research at MIT at age 14 (00:09:24)Dropping out of High School and Starting Thiel Fellowship at age 17 (00:10:36)MIT ISN Lab (00:11:09) https://isn.mit.edu/Evaluating ARM Processors for High Performance Computing (00:11:28) https://en.wikipedia.org/wiki/ARM_architecture_familyARM Calxeda Processor (00:11:38) https://en.wikipedia.org/wiki/Calxedahttps://www.zdnet.com/article/what-the-death-of-calxeda-means-for-the-future-of-microservers/Scaling Out Low Power Processors for Data Center Compute (00:12:27)Incorporating REX Computing (00:13:42) http://rexcomputing.com/https://fortune.com/2015/07/21/rex-computing/Facebook and the Open Compute Project (00:14:18) https://www.opencompute.org/Deciding Against Arm (00:14:49)ARMv8 (00:15:12) https://en.wikichip.org/wiki/arm/armv8Deciding to Design a New Architecture (00:16:26)Multiflow (00:18:23) https://en.wikipedia.org/wiki/MultiflowGood Architecture Ideas from the Past (00:18:35)Thomas' Talk at Stanford (00:18:59) https://youtu.be/ki6jVXZM2XURISC vs. CISC Debate (00:19:37) https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/SPARC Instruction Set (00:20:04) https://en.wikipedia.org/wiki/SPARCThe Importance of History (00:20:58)RISC Came Before CISC (00:23:08)CDC 6600 (00:23:20) https://en.wikipedia.org/wiki/CDC_6600Load-Store Architecture (00:23:53) https://en.wikipedia.org/wiki/Load–store_architectureIBM System/360 (00:24:02) https://en.wikipedia.org/wiki/IBM_System/360PowerPC (00:24:29) https://en.wikipedia.org/wiki/PowerPCVLIW (00:25:02) https://en.wikipedia.org/wiki/Very_long_instruction_wordELI-512 and Josh Fisher (00:25:05) https://dl.acm.org/doi/pdf/10.1145/800046.801649https://en.wikipedia.org/wiki/Josh_FisherFloating Point Systems, Inc. (FPS) (00:26:45) https://en.wikipedia.org/wiki/Floating_Point_SystemsMultiflow Compiler (00:26:52) https://www.cs.yale.edu/publications/techreports/tr364.pdfInstruction Level Parallelism (00:27:33) https://en.wikipedia.org/wiki/Instruction-level_parallelismIntel Itanium (00:28:20) https://en.wikipedia.org/wiki/ItaniumItanium is not a VLIW Architecture (00:29:04)Explicitly Parallel Instruction Computer (EPIC) (00:29:22) https://en.wikipedia.org/wiki/Explicitly_parallel_instruction_computingx86 and Pentium (00:30:18) https://en.wikipedia.org/wiki/X86https://en.wikipedia.org/wiki/PentiumImpact of Branch Prediction and Caching on Determinism (00:31:34) https://en.wikipedia.org/wiki/Branch_predictorhttps://en.wikipedia.org/wiki/CPU_cacheWhy Itanium Failed (00:32:27)REX's NEO Architecture (00:35:29) http://rexcomputing.com/#neoarchHard Real-Time Determinism (00:35:41)Scratchpad Memory (00:35:54) https://en.wikipedia.org/wiki/Scratchpad_memoryRemoving Memory Management (TLB, MMU, etc.) (00:36:18) https://en.wikipedia.org/wiki/Translation_lookaside_bufferhttps://en.wikipedia.org/wiki/Memory_management_unitALU, FPU, and Register Files (00:37:14) https://en.wikipedia.org/wiki/Arithmetic_logic_unithttps://en.wikipedia.org/wiki/Floating-point_unithttps://en.wikipedia.org/wiki/Register_fileBenefits of Removing Implicit Caching Layers (00:38:30)VLIW in Signal Processing (00:39:51) https://en.wikipedia.org/wiki/Digital_signal_processorVLIW Won in a Silent Way (00:40:49)Original Reason for Hardware-Managed Caching (00:41:26)Impact of VLIW and Software-Managed Memory on Compile T

    1h 23m
  2. 02/14/2024

    1: Philip Freidin

    Philip Freidin joins to talk about developing a passion for electronics and computer architecture while growing up in Australia, getting started on the PDP-8, his grand plan to work on AMD bit-slice processors, and plenty more. Philip on X: https://twitter.com/PhilipFreidin Philip’s Site: http://www.fliptronics.com/ Show Notes Welcome Philip Freidin (00:01:02)Growing up in Australia (00:03:25)Teletype Model 33 ASR (00:07:10)https://en.wikipedia.org/wiki/Teletype_Model_33Kilocore Ticks (00:09:15)General Electric GE-235 (00:11:50)https://en.wikipedia.org/wiki/GE-200_serieshttps://www.computerhistory.org/revolution/mainframe-computers/7/178/720Learning Fortran and Algol (00:16:03)https://en.wikipedia.org/wiki/Fortranhttps://en.wikipedia.org/wiki/ALGOLPeeling Back Abstractions (00:19:02)Working on Hospital Electronics (00:19:51)Making a Digital Clock at Age 14 (00:24:31)DEC PDP-8 (00:26:26)https://en.wikipedia.org/wiki/PDP-8Why DEC Used the PDP Name (00:29:40)https://en.wikipedia.org/wiki/Programmed_Data_ProcessorGlass Teletypes (00:31:01)Programming in FOCAL and Fortran (00:31:31)https://en.wikipedia.org/wiki/FOCAL_(programming_language)Linking and Loading with Paper Tape (00:33:27)https://en.wikipedia.org/wiki/Punched_tapeDECtape (00:35:57)https://en.wikipedia.org/wiki/DECtapeDesigning a Floppy Disk Drive System for PDP-8 (00:37:01)PDP-8 OMNIBUS Backplane (00:37:38)https://gunkies.org/wiki/OMNIBUSSoftware Support for Floppy Disk Drive (00:39:42)OS/8 Operating System (00:40:26)https://en.wikipedia.org/wiki/OS/8DEC Manuals (00:43:53)https://bitsavers.org/pdf/dec/The Onion Model for Abstraction (00:45:21)Understanding Computer Architecture (00:48:29)Moving to the PDP-11 (00:52:31)https://en.wikipedia.org/wiki/PDP-11PDP-11/34 and Microcode (00:54:36)https://gunkies.org/wiki/PDP-11/3474181 ALU Chip (00:54:49)https://en.wikipedia.org/wiki/74181DEC VAX 11/780 (00:55:29)https://gunkies.org/wiki/VAX-11/78074182 Chip (00:57:55)https://www.ti.com/lit/ds/symlink/sn54s182.pdfPerformance Optimization by Understanding Dependencies (01:00:01)DSP and FPGAs (01:01:06)https://en.wikipedia.org/wiki/Field-programmable_gate_arrayhttps://en.wikipedia.org/wiki/Digital_signal_processingFIR Filter (01:05:12)https://en.wikipedia.org/wiki/Finite_impulse_responseTMS320 (01:06:16)https://en.wikipedia.org/wiki/TMS320Tradeoffs Between DSP Chips and FPGAs (01:11:46)Applications of FIR Filters (01:13:38)FPGAs in Communication Systems (01:15:28)Optimization Starts with Algorithms (01:16:20)Misuse of Floating Point (01:16:55)https://en.wikipedia.org/wiki/Floating-point_unitJoining AMD (01:18:57)Bit Slice (01:19:53)https://en.wikipedia.org/wiki/Bit_slicingIntel 3002 (01:20:52)https://www.cpu-zone.com/3002/intel3002.pdfMMI 6701 (01:21:00)https://www.cpushack.com/2011/03/31/cpu-of-the-day-mmi-6701-bit-slice/AMD Am2901 (01:22:16)https://www.righto.com/2020/04/inside-am2901-amds-1970s-bit-slice.htmlData General Eclipse MV/8000 (01:23:24)https://en.wikipedia.org/wiki/Data_General_Eclipse_MV/8000Mini Supercomputers (01:24:13)https://en.wikipedia.org/wiki/MinisupercomputerDesigning first chip at age 12 (01:25:11)RS Latch (01:28:03)https://www.allaboutcircuits.com/textbook/digital/chpt-10/s-r-latch/74LS279 (01:28:39)https://www.ti.com/lit/ds/symlink/sn74ls279a.pdfLearning about Bit Slice (01:30:00)R&D Electronics (01:30:53)Internal and External Applications Engineers (01:32:45)Becoming Australia’s First Field Applications Engineer (01:36:11)MMI Programmable Array Logic (PAL) (01:37:08)https://en.wikipedia.org/wiki/Programmable_Array_LogicMeeting the Bit Slice Designers (01:38:03)S-100 Bus (01:39:01)https://en.wikipedia.org/wiki/S-100_busTeaching at University (01:39:50)Sending Resume to AMD (01:42:27)AMD Interview (01:43:16)Moving to the U.S. (01:45:40)AMD’s Secret RISC CPU (01:46:19)Am29000 (01:50:19)https://en.wikipedia.org/wiki/AMD_Am29000Why RISC over CISC? (01:51:38)https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/Memory is free (01:52

    2h 33m

Ratings & Reviews

5
out of 5
3 Ratings

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The art, science, and history of processor design.

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