Tecnología

World of FPGA Podcast

1

World of FPGA Podcast

David Kirchner
Top Noticias Tech

2

Top Noticias Tech

Tech Santos
The Interface

3

The Interface

BBC
La Vuelta a la Manzana

4

La Vuelta a la Manzana

Cristo Fernando Vega Quevedo
overFLOW - noticias tech a diario

5

overFLOW - noticias tech a diario

Jesús Veliz @jevedel
Ham Radio Workbench Podcast

6

Ham Radio Workbench Podcast

Ham Radio Workbench
Al otro lado del micrófono

7

Al otro lado del micrófono

Jorge Marín Nieto

HACE 1 DÍA

1

Siri se Retrasa MÁS?!

TNT 228 - Top Noticias Tech con Tech Santos. Show semanal dedicado a las noticias de tecnología mas relevantes. Hosted on Acast. See acast.com/privacy for more information.

hace 1 día

•

1 h y 45 min
HACE 5 DÍAS

2

Charla Tech con Edu Sánchez @soyedusanchez

Conoce a Edu Sanchez: Youtube: https://www.youtube.com/channel/UCNK9bNf-XenQUagG10LuAfA Twitter deEdu:@soyedusanchez ÚNETE al MEJOR CANAL de APPLE y TECNOLOGÍA: https://cutt.ly/hjErCTP MIS CÓDIGOS DE DESCUENTO 💻Parallels: https://prf.hn/click/camref:1100lq3Kt/creativeref:1011l52541 👻VPN Cyberghost: https://www.cyberghostvpn.com/offer/CristoVega_2cb02dcl 📲PaperLike: paperlike.com/CristoVQ 📦 COMPRAS EN AMAZON( afiliado): https://amzn.to/36xlnzA 🔸MIS REDES📲 https://beacons.ai/cristovega 📹 “La Morada” 🟣 Twitch: https://www.twitch.tv/cristovegaoficial 🔰 VIP ➡️ https://www.patreon.com/CristoVega

hace 5 días

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43 min
6 FEB

3

Empieza la Guerra de IA

TNT 227 - Top Noticias Tech con Tech Santos. Show semanal dedicado a las noticias de tecnología mas relevantes. Hosted on Acast. See acast.com/privacy for more information.

6 feb

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1 h y 37 min
30/09/2025

4

WFP032 – FPGA Routing

.avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP032 – FPGA Routing @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 32 of the World of FPGA Podcast. We have an internal digital highway inside an FPGA to connect all the different blocks. This highway has a lot of interesting features. Content of this Episode Routing Resources Connection lines Connection boxes Switching boxes But it depends Routing process Routing Algorithms Routing key challenges Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP032 – FPGA Routing appeared first on World of FPGA by David Kirchner.

30/09/2025

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17 min
16/09/2025

5

WFP031 – FPGA Memory

.avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP031 – FPGA Memory @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 31 of the World of FPGA Podcast. Memory is essential for a lot of things in your FPGA design. And FPGAs have a lot of different memory. Content of this Episode Flip-Flops SRAM blocks Ultra RAM Flash Memory High Bandwidth Memory Memory-Controller External Memory Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP031 – FPGA Memory appeared first on World of FPGA by David Kirchner.

16/09/2025

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11 min
14/10/2025

6

WFP033 – FPGA I/Os

.avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP033 – FPGA I/Os @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 33 of the World of FPGA Podcast. Signals have to get into the FPGA and out of the FPGA. Here we need input/output pins. Here we will have a closer look. Content of this Episode I/O pad Logic block I/O standards Single-Ended Standards Differential Standards Key Considerations for I/O Standards Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP033 – FPGA I/Os appeared first on World of FPGA by David Kirchner.

14/10/2025

•

17 min
HACE 1 DÍA

7

¿Desbloqueamos LATAM GPT o bloqueamos las redes sociales a los menores? | OVERFLOW 140226

🎙️ ¡Te doy la bienvenida a overFLOW, resumen semanal para este sábado, 14 de febrero de 2026! 🚀 Un recorrido por la soberanía digital, la infancia hiperconectada y el futuro de los plegables. 🤖 Latam-GPT y la soberanía regional. América Latina presentó su propio modelo basado en Llama 3.1 con 70B parámetros y más de 300 mil millones de tokens regionales, impulsado desde Chile con apoyo multilateral y enfoque en contexto cultural, lenguas originarias y servicios públicos. No compite en potencia bruta con los gigantes globales, pero sí apuesta por identidad y datos propios, mientras proyectos como Artificio en Perú muestran que la ventaja también puede estar en desarrollar tecnología desde problemas locales únicos. ¿Estamos ante el inicio de una IA verdaderamente latinoamericana o frente a un gesto estratégico con límites técnicos claros? 📵 Menores y el muro digital. Países como Australia avanzan con bloqueos a redes sociales para menores de 16, Europa endurece verificación de edad y el debate se centra en diseño adictivo, salud mental y exposición a contenido extremo. La evidencia científica muestra riesgos reales —ansiedad, depresión, pérdida de sueño— pero también beneficios cuando el uso es activo y comunitario. Entre prohibición total y educación digital, la pregunta ya no es si afectan, sino cómo regular sin aislar. ¿Proteger o prohibir: cuál es el equilibrio correcto para una generación que ya nació conectada? 📱 Samsung y el giro hacia el fold grande. Con el Unpacked del 25 de febrero en el horizonte, crece la expectativa por la siguiente fase de Galaxy AI, mientras estudios proyectan que en 2026 los plegables tipo libro dominarán hasta el 65% del mercado, dejando atrás al formato clamshell. La preferencia por productividad y especificaciones premium está redefiniendo el segmento, incluso antes de que Apple entre oficialmente al juego. ¿Será este el año en que el plegable deje de ser experimento y se convierta en estándar de gama alta? ✨ ¡Descubre estas historias y acompáñame en este recorrido donde el mundo de la tecnología gira más rápido que este! 🌟

hace 1 día

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46 min
22/07/2025

8

WFP030 – FPGA Conference 2025

.avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP030 – FPGA Conference 2025 @keyframes av_boxShadowEffect_av-lbdasn2o-abb509c548ba3aacb3b3a870404a7702 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-abb509c548ba3aacb3b3a870404a7702 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-abb509c548ba3aacb3b3a870404a7702 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 30 of the World of FPGA Podcast. It was time for a little trip again. I went to Munich to the three-day FPGA conference of PLC2 and the Vogel Verlag. Content of this Episode 3 day FPGA Conference in Munich FPGA Conference the biggest event in Europe Some facts 3 days 430 Participants 128 Lectures 110 Speakers 39 Exhibitors This year triple anniversary 40 years FPGA 30 years PLC2 10 years FPGA Conference All my visited talks Welcome to the Post-European Cyber Resilience Act (CRA) Era FPGAs and the Cyber Resilience Act Cyber Resilience Act: Planning your Security Future Making Simple FPGA Testbenches – Utilising Important Quality Measures A Cuckoo Hash-Based CAM Architecture for FPGA and ASIC Implementations Elevate your Design: Security and Power Efficiency with AMD Spartan UltraScale+ FPGAs Faster Change of Probe Signals using the Vivado Logic Analyzer Warning! Your FPGAs & SoC FPGAs are Under Attack Functional Safety for Hardware and Software Security, Regulations and FPGA-Based Systems – How to Make Your System Secure Verify the Bits that Fly : A Demonstration of Bitstream to HDL Equivalence Checking Why VUnit? Managing and Versioning Gateware Source Code on Git with Hog A Baseboard Management Controller for FPGA/SoC Board Supervision and Faster Bringup GateMate FPGA: Qualification for Radiation-Tolerant Applications GateMate FPGA: High-Speed Transceiver (SerDes) Hands-On Project-Based and Non-Project-Based Scripting in Vivado Multi-Run Management Using Vivado How to Drive Parallel High-Speed Circuits from an AMD FPGA Next FPGA conference is from 30 June – 2 July 2026 Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP030 – FPGA Conference 2025 appeared first on World of FPGA by David Kirchner.

22/07/2025

•

35 min
17/06/2025

9

WFP029 – FPGA DSP

.avia-section.av-1apwy4-f0a9c875d3b2ecccb308559719541ff4 .av-extra-border-element .av-extra-border-inner{ background-color:#39342d; } .flex_column.av-xm6p0-62c5e21bb4b433b2eebb2ac41c4e9edd{ border-radius:10px 10px 10px 10px; padding:10px 10px 10px 10px; } #top .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2{ padding-bottom:10px; } body .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-special-heading-tag .heading-char{ font-size:25px; } .av-special-heading.av-lbda955k-6396b2ee9d9c24f957e8b7636dd41ea2 .av-subheading{ font-size:15px; } WoF Podcast WFP029 – FPGA DSP @keyframes av_boxShadowEffect_av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 { 0% { box-shadow: 0 0 0 0 ; opacity: 1; } 100% { box-shadow: 0 0 10px 0 ; opacity: 1; } } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 img.avia_image{ box-shadow: 0 0 10px 0 ; } .avia-image-container.av-lbdasn2o-c7eec03b1056dd0cbbc328c4d0577502 .av-image-caption-overlay-center{ color:#ffffff; } Shownotes Episode 29 of the World of FPGA Podcast. How can FPGAs calculate so fast? The secret inside an FPGA is a digital signal processing block. Content of this Episode What does DSP stand for? Common parts inside an DSP block Function representation Important facts Newsletter #mailpoet_form_1 .mailpoet_form { } #mailpoet_form_1 .mailpoet_column_with_background { padding: 10px; } #mailpoet_form_1 .mailpoet_form_column:not(:first-child) { margin-left: 20px; } #mailpoet_form_1 .mailpoet_paragraph { line-height: 20px; margin-bottom: 20px; } #mailpoet_form_1 .mailpoet_segment_label, #mailpoet_form_1 .mailpoet_text_label, #mailpoet_form_1 .mailpoet_textarea_label, #mailpoet_form_1 .mailpoet_select_label, #mailpoet_form_1 .mailpoet_radio_label, #mailpoet_form_1 .mailpoet_checkbox_label, #mailpoet_form_1 .mailpoet_list_label, #mailpoet_form_1 .mailpoet_date_label { display: block; font-weight: normal; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea, #mailpoet_form_1 .mailpoet_select, #mailpoet_form_1 .mailpoet_date_month, #mailpoet_form_1 .mailpoet_date_day, #mailpoet_form_1 .mailpoet_date_year, #mailpoet_form_1 .mailpoet_date { display: block; } #mailpoet_form_1 .mailpoet_text, #mailpoet_form_1 .mailpoet_textarea { width: 200px; } #mailpoet_form_1 .mailpoet_checkbox { } #mailpoet_form_1 .mailpoet_submit { } #mailpoet_form_1 .mailpoet_divider { } #mailpoet_form_1 .mailpoet_message { } #mailpoet_form_1 .mailpoet_form_loading { width: 30px; text-align: center; line-height: normal; } #mailpoet_form_1 .mailpoet_form_loading > span { width: 5px; height: 5px; background-color: #5b5b5b; }#mailpoet_form_1{border-radius: 0px;text-align: left;}#mailpoet_form_1 form.mailpoet_form {padding: 20px;}#mailpoet_form_1{width: 100%;}#mailpoet_form_1 .mailpoet_message {margin: 0; padding: 0 20px;}#mailpoet_form_1 .mailpoet_paragraph.last {margin-bottom: 0} @media (max-width: 500px) {#mailpoet_form_1 {background-image: none;}} @media (min-width: 500px) {#mailpoet_form_1 .last .mailpoet_paragraph:last-child {margin-bottom: 0}} @media (max-width: 500px) {#mailpoet_form_1 .mailpoet_form_column:last-child .mailpoet_paragraph:last-child {margin-bottom: 0}} Please leave this field empty When clicking on the button "Let's go..." I agree to the terms and conditions laid out in the Privacy Policy Check your inbox or spam folder to confirm your subscription. Follow us Follow our LinkedIn World of FPGA Page Intro- and outro music The music for intro and outro is provided by Cedric Galke x Fachhochschule Dortmund with the title Happy Dance under free license. The post WFP029 – FPGA DSP appeared first on World of FPGA by David Kirchner.

17/06/2025

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9 min
03/10/2022

10

Advantages of Near Flash Computing with Arvind

CSAIL Professor Arvind details his work in near-storage computing. He explains how he's using flash storage instead of massive amounts of DRAM for big data problems. A transcript of this podcast will be available at cap.csail.mit.edu

03/10/2022

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28 min

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